Dear customers,
About the change in the name such as "Oki Electric Industry Co. Ltd." and
"OKI" in documents to OKI Semiconductor Co., Ltd.
The semiconductor business of Oki Electric Industry Co., Ltd. was succeeded to OKI
Semiconductor Co., Ltd. on October 1, 2008.
Therefore, please accept that although
the terms and marks of "Oki Electric Industry Co., Ltd.", “Oki Electric”, and "OKI"
remain in the documents, they all have been changed to "OKI Semiconductor Co., Ltd.".
It is a change of the company name, the company trademark, and the logo, etc. , and
NOT a content change in documents.
October 1, 2008
OKI Semiconductor Co., Ltd.
550-1 Higashiasakawa-cho, Hachioji-shi, Tokyo 193-8550, Japan
http://www.okisemi.com/en/
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¡ Semiconductor
MSM54V24616
¡ Semiconductor
131,072-Word
¥
16-Bit
¥
2-bank SYNCHRONOUS DYNAMIC RAM
MSM54V24616
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DESCRIPTION
The MSM54V24616 is a 131,072-word
¥
16-bit
¥
2-bank synchronous dynamic RAM, fabricated
in OKI's CMOS silicon gate process technology. The device operates at 3.3 V. The inputs and
outputs are LVTTL compatible. This device can operate up to 125MHz by using synchronous
interface.
FEATURES
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131,072-words
¥
16-bit
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2 banks configuration
Single 3.3 V±10% power supply
LVTTL compatible inputs and outputs
All input signals are latched at rising edge of system clock
Auto precharge and controlled precharge
Internal pipelined operation: column address can be changed every clock cycle
Dual internal banks controlled by A9 (Bank Address: BA)
Independent byte operation via DQML and DQMU
Programmable burst sequence (Sequential / Interleave)
Programmable burst length (1, 2, 4, 8 and full page)
Programmable
CAS
latency (1, 2 and 3)
Programmable Write burst (Burst write / Single write)
Burst stop function (full-page burst)
Power Down operation and Active Power Down (Clock Suspend) operation
Auto refresh and Self refresh capability
Refresh period: 1,024 cycles / 16 ms
Package options:
50-pin plastic TSOP (type II)
(TSOPII50-P-400-0.80-K) (Product : MSM54V24616-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Family
MSM54V24616-8
MSM54V24616-10
MSM54V24616-12
Max.
Frequency
125 MHz
100 MHz
83MHz
Access Time (Max.)
t
AC1
22 ns
27 ns
32 ns
t
AC2
10 ns
12 ns
15 ns
t
AC3
7 ns
9 ns
10 ns
Power Dissipation
Operating (Max.) Standby (Max.)
648 mW
540 mW
468 mW
7.2 mW
1
MSM54V24616
¡ Semiconductor
PIN CONFIGURATION (TOP VIEW)
V
CC
DQ0
DQ1
V
SS
(Q)
DQ2
DQ3
V
CC
(Q)
DQ4
DQ5
V
SS
(Q)
DQ6
DQ7
V
CC
(Q)
DQML
WE
CAS
RAS
CS
A9
A8
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
V
SS
49
DQ15
48
DQ14
47
V
SS
(Q)
46
DQ13
45
DQ12
44
V
CC
(Q)
43
DQ11
42
DQ10
41
V
SS
(Q)
40
DQ9
39
DQ8
38
V
CC
(Q)
37
NC
36
DQMU
35
CLK
34
CKE
33
NC
32
NC
31
NC
30
A7
29
A6
28
A5
27
A4
26
V
SS
50-Pin Plastic TSOP (II)
(K Type)
Pin Name
CLK
CS
CKE
A0 - A8
A9
RAS
CAS
WE
Function
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Pin Name
DQML / DQMU
DQ0 - DQ15
V
CC
V
SS
V
CC
(Q)
V
SS
(Q)
NC
Function
Data Input/Output Mask
Data Input/Output
Power Supply (3.3 V)
Ground (0 V)
Data Output Power Supply (3.3 V)
Data Output Ground (0 V)
No Connection
Note:
The same power supply voltage must be provided to every V
CC
pin and V
CC
(Q)pin.
The same GND voltage level must be provided to every V
SS
pin and V
SS
(Q) pin.
3
¡ Semiconductor
MSM54V24616
PIN DESCRIPTION
CLK
CS
CKE
Fetches all inputs at the "H" edge.
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,
DQMU and DQML.
Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked that the subsequent CLK operation is deactivated.
CKE should be asserted at least one cycle prior to a new command.
Address
Row & column multiplexed.
Row address: RA0 - RA8
Column address: CA0 - CA7
A9
RAS
CAS
WE
DQML
DQMU
DQ0 - DQ15
Masks the read data of two clocks later when DQMU / DQML is set "H" at the "H" edge of the clock signal.
Masks the write data of the same clock when DQMU / DQML is set "H" at the "H" edge of the clock signal.
Data inputs/outputs are multiplexed on the same pin.
Functionality depends on the combination. For details, see the function truth table.
Selects bank to be activated during row address latch time and selects bank for precharge and read/
write during column address latch time. A9= "L" : Bank A, A9= "H" : Bank B
3
MSM54V24616
¡ Semiconductor
BLOCK DIAGRAM
CKE
CLK
CS
RAS
CAS
WE
DQML
DQMU
Timing
Register
Progra-
ming
Register
Latency
& Burst
Controller
I/O
Controller
Bank
Controller
A9
A0-A9
Internal
Col.
Address
Counter
Input
Data
Register
8
Input
Buffers
16
16
8
Column
Address
Buffers
Column Decoders
Sense Amplifier
Internal
Row
Address
Counter
16
Read
Data
Register
16
16
Output
Buffers
DQ0-DQ15
Row
Decoders
Word
Drivers
2Mb
Memory
Cells
2Mb
Memory
Cells
9
Row
Address
Buffers
9
Row
Decoders
Word
Drivers
Sense Amplifier
Column Decoders
5
