E2U0019-28-81
¡ Semiconductor
MSM7507-01/02/03
¡ Semiconductor
Single Rail CODEC
This version: Aug. 1998
MSM7507-01/02/03
Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM7507 is a single-channel CODEC CMOS IC for voice signals ranging from 300 to 3400
Hz with filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, the device is
optimized for ISDN terminals, digital wireless systems, and digital PBX systems.
The device uses the same transmission clocks as those used in the MSM7508B and MSM7509B.
The analog output signal, which is of a differential type and can drive a 600
W
load, can directly
drive a handset receiver.
FEATURES
• Single power supply: +5 V
±5%
• Low power consumption
Operating mode:
20 mW Typ. 40 mW Max. V
DD
= 5 V
Power down mode:
0.03 mW Typ. 0.3 mW Max. V
DD
= 5 V
• ITU-T Companding law
MSM7507-01:
m/A-law
pin selectable
MSM7507-02:
m-law
MSM7507-03: A-law
• Transmission characteristics conforms to ITU-T G.714
• Built-in PLL eliminates a master clock
• Serial data rate: 64/128/256/512/1024/2048 kHz
96/192/384/768/1536/1544/200 kHz
• Adjustable transmit gain
• Adjustable receive gain
• Built-in reference voltage supply
• Analog output can directly drive a 600
W
line transformer
• The 24-Pin SOP package products provide pin compatibility with the MSM7543/7544
• The 20-Pin SSOP package products have 1/3 the foot print of conventional products
• Package options:
24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM7507-01GS-K)
(Product name : MSM7507-02GS-K)
(Product name : MSM7507-03GS-K)
20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name : MSM7507-01MS-K)
(Product name : MSM7507-02MS-K)
(Product name : MSM7507-03MS-K)
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¡ Semiconductor
MSM7507-01/02/03
BLOCK DIAGRAM
AIN–
AIN+
GSX
–
+
RC
LPF
8th
BPF
AD
CONV.
AUTO
ZERO
PCMOUT
TCONT
PLL
XSYNC
BCLK
SGC
SG
SG
GEN
VR
GEN
RTIM
RSYNC
(ALAW)
PCMIN
PDN
V
DD
AG
DG
VFRO
PWI
AOUT–
–
+
SG
5th
LPF
DA
CONV.
RCONT
PWD
Logic
PWD
–
+
–
+
SG
AOUT+
SG
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¡ Semiconductor
MSM7507-01/02/03
PIN CONFIGURATION (TOP VIEW)
SG 1
AOUT+ 2
AOUT– 3
NC 4
PWI 5
VFRO 6
NC 7
V
DD
8
DG 9
PDN 10
RSYNC 11
PCMIN 12
24 SGC
23 AIN+
22 AIN–
21 GSX
20 NC
19 NC
18 (ALAW)*
17 NC
16 AG
15 BCLK
14 XSYNC
13 PCMOUT
SG 1
AOUT+ 2
AOUT– 3
PWI 4
VFRO 5
V
DD
6
DG 7
PDN 8
RSYNC 9
PCMIN 10
20 SGC
19 AIN+
18 AIN–
17 GSX
16 NC
15 (ALAW)*
14 AG
13 BCLK
12 XSYNC
11 PCMOUT
NC : No connect pin
20-Pin Plastic SSOP
NC : No connect pin
24-Pin Plastic SOP
* The ALAW pin is only applied to the MSM7507-01GS-K/MSM7507-01MS-K.
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¡ Semiconductor
MSM7507-01/02/03
PIN AND FUNCTIONAL DESCRIPTIONS
AIN+, AIN–, GSX
Transmit analog input and transmit level adjustment.
AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is
connected to the output of the op-amp and is used to adjust the level, as shown below.
When not using AIN– and AIN+, connect AIN– to GSX and AIN+ to SG. During power saving
and power down modes, the GSX output is at AG voltage.
1) Inverting input type
C1
Analog input
R1
GSX
AIN–
AIN+
SG
R1 : variable
R2 > 20 kW
C1 > 1/(2
¥
3.14
¥
30
¥
R1)
Gain = R2/R1
£
10
R2
–
+
2) Non inverting input type
C2
Analog input
R5
R4
R3
AIN+
AIN–
GSX
SG
+
–
R3 > 20 kW
R4 > 20 kW
R5 > 50 kW
C2 > 1/ (2
¥
3.14
¥
30
¥
R5)
Gain = 1 + R4 / R3
£
10
AG
Analog signal ground.
VFRO
Receive filter output.
The output signal has an amplitude of 2.4 V
PP
above and below the signal ground voltage (SG)
when the digital signal of +3 dBmO is input to PCMIN and can drive a load of 20 kW or more.
For driving a load of 20 kW or less, connect a resistor of 20 kW or more between the pins VFRO
and PWI.
When adding the frequency characteristics to the receive signal, refer to the application example.
During power saving or power down mode, the output of VFRO is at the voltage level of SG.
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¡ Semiconductor
PWI, AOUT+, AOUT–
MSM7507-01/02/03
PWI is connected to the inverting input of the receive driver. The receive driver output is
connected to the AOUT– pin. Therefore, the receive level can be adjusted with the pins VFRO,
PWI, and AOUT–. When the PWI pin is not used, connect the PWI pin to the AOUT– pin, and
leave open the pins AOUT– and AOUT+. The output of AOUT+ is inverted with respect to the
output of AOUT–. Since the signal from which provides differential drive of an impedance of 1.2
kW, these outputs can directly be connected to a receiver of handset using a piezoelectric
earphone. Refer to the application example.
VI
Receive Filter
VFRO
PWI
R6
R7
R6 > 20 kW
ZL
≥
1.2 kW
Gain = VO/VI = 2
¥
R7/R6
£
2
SG
–
+
AOUT–
VO
ZL
SG
–
+
AOUT+
During power saving and power down modes, the outputs of AOUT+ and AOUT– are in a high
impedance state.
The electrical driving capability of the AOUT– pin and AOUT+ pin is
±1.3
V maximum. The
output load resistor has a minimum value of 0.6 kW.
If an output amplitude less than
±1.3
V is allowed, these outputs can drive a load resistance less
than that described above. For more details, refer to SINGLE POWER SUPPLY PCM CODEC
APPLICATION NOTE.
V
DD
Power supply for +5 V.
PCMIN
PCM signal input.
A serial PCM signal input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLK signal.
The data rate of the PCM signal is equal to the frequency of the BCLK signal.
The PCM signal is shifted at a falling edge of the BCLK signal and latched into the internal register
when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
BCLK
Shift clock signal input for the PCMIN and PCMOUT signal.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048,
or 200 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the
power saving state.
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