E2U0034-28-82
¡ Semiconductor
MSM7586-01/03
¡ Semiconductor
p/4
Shift QPSK MODEM/ADPCM CODEC
This version: Aug. 1998
MSM7586-01/03
Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM7586 is a CMOS IC developed for use with digital cordless telephones. The device
provides a
p/4
shift QPSK modem function and a CODEC function which performs transcoding
between the voice band analog signal and 32 kbps ADPCM data.
The MSM7586 performs DTMF tone and several types of tone generation, transmit/receive data,
mute and gain control, side-tone pass and its gain control, and VOX function.
FEATURES
(p/4 Shift QPSK Modem Unit)
• 384 kbps transmission speed
• Built-in root Nyquist digital filter for the baseband band limiter
• Built-in D/A converters for the analog outputs of the quadrature signal component I and Q
• The DC offset and gain can be adjusted with respect to the differential I and Q analog outputs
• Completely digitized
p/4
shift QPSK demodulator system
(ADPCM CODEC Unit)
• ADPCM system: built-in ITU-T Recommendations G.726 (32kbps, 24 kbps, 16 kbps)
• Transmit/receive full-duplex capability
• PCM interface code format: selectable between
m-law
and A-law
• Serial ADPCM and PCM transmission rate: 64 kbps to 2,048 kbps
• Transmit/receive mute function; transmit/receive programmable gain setting
• Side tone generator (8-step level adjustment)
• Built-in DTMF tone, ringing tone, and various ringing tone generators
• Built-in VOX function
(Common Unit)
• Operate with a single 3 V power supply (V
DD
: 2.7 V to 3.6 V)
• Low power consumption
When entire system is operating: 20 mA Typ.
When powered down:
0.02 mA Typ.
• Package:
100-pin plastic TQFP (TQFP100-P-1414-0.50-K) (Product name: MSM7586-01TS-K)
(Product name: MSM7586-03TS-K)
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¡ Semiconductor
MSM7586-01/03
BLOCK DIAGRAM
VDDM
VDAM
RXSC
SL1
SL2
DGM
AGM
PDN0
PDN1
PDN2
IFIN
AFC
RXD
Phase
detector
Delay
detector
AFC
Decision
RXC
MCK
IFCK
SL1
DEC
SL2
DPLL
X2
To each block
RPR
X1
EXCKM
DENM
DINM
DOUTM
R7, R6
R5, R4
I+
I–
Q+
Q–
4
CRM1-B7 to B4
+1
MODEM
MCU
interface
RCW
To each block
SLS
BSTO
LPF
–1
+1
D/A
DC Adjust
LPF
ATT
CRM1-B3 to B0
Root Nyquist LPF
D/A
S/P
MAPPING
TXD
TXW
–1
DC Adjust
ATT
3.84M
To D/A
CRM0-B6
PLL
TXCI
SGM
SGCR
Receiver
R
VREF
<MODEM Unit>
<CODEC Unit>
1/10
384k
TXCO
SGCT
IO1
IO2
AIN1–
AIN1+
GSX1
AIN2–
SW1
CRC5-B7
CRC5-B6
Transmitter
T
VDAC
VOICE
DETECT
ADPCM
CODER
P
/
S
S
/
P
P
/
S
S
/
P
P
/
S
S
/
P
VOXO
XSYNC
IS
PCMSI
PCMSO
BCLK
PCMRI
PCMRO
IR
RSYNC
EXCKC
DENC
DINC
DOUTC
SW2
–
+
–
+
T
RC
Filter
A/D
Convertor
CRC4-B6
CRC2-B6 to B4
BPF
GSX2
AOUT+
–1
ATT
COMPA
NDER
DTMF
/Tone
Generator
ATT
R
AOUT–
PWI
VFRO
SAO
AIN3
GSX3
AIN4
GSX4
–
+
Sign bit
CRC3-B3 to B0
CRC2-B2 to B0
CRC3-B7 to B5
CRC4-B5
RC
Filter
D/A
Convertor
LPF
+
+
ATT
EXPAN
DER
To each
block
ADPCM
DE-
CODER
–
+
R
Noise
generator
CRC5-B5
CRC5-B4
Power detect
To each
block
CODEC
MCU
interface
–
+
T
SW3
SW4 SW5
VDDC
VDAC
DGC
AGC
PDN3
VOXI
IO3
IO4
IO5
IO6
IO7
TOUT1
TOUT2
TOUT3
RESET
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¡ Semiconductor
MSM7586-01/03
PIN CONFIGURATION (TOP VIEW)
DOUTM
77
EXCKM
100 VDDM
RXSC
DENM
PDN0
PDN1
PDN2
RCW
MCK
IFCK
RPR
RXD
RXC
SLS
IFIN
AFC
NC
NC
NC
99
98
97
96
95
94
93
92
91
90
89
88
87
86
NC
X1
X2
85
84
83
82
81
80
79
78
VDAM
Q–
Q+
I–
I+
NC
SGM
AGM
AGC
SGCR
SGCT
AIN1+
AIN1–
GSX1
IO5
IO6
IO7
AIN2
GSX2
IO1
IO2
VFRO
PWI
AOUT–
AOUT+
76
DINM
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
TXW
TXD
TXCO
TXCI
NC
BSTO
DGM
DGC
R7
R6
R5
R4
NC
BCLK
XSYNC
RSYNC
NC
PCMSO
PCMSI
IS
NC
IR
PCMRO
PCMRI
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
VOXI
DOUTC
TOUT1
TOUT2
TOUT3
VDDC
PDN3
GSX4
RESET
VDAC
DINC
AIN3
AIN4
EXCKC
NC : No connect pin
100-Pin Plastic TQFP
VOXO
GSX3
IO3
IO4
DENC
SAO
NC
NC
NC
NC
NC
50
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¡ Semiconductor
MSM7586-01/03
PIN AND FUNCTIONAL DESCRIPTIONS
(Modem
Unit)
TXD
Transmit data input for 384 kbps.
TXCI
Transmit clock input.
When the control register CRM0 - B6 is "0", a 384 kHz clock pulse synchronous with TXD should
be input to this pin. This clock pulse should be continuous because this device use APLL to
generate an internal clock pulse.
When CRM0 - B6 is "1", a 3.84 MHz clock pulse should be input to this pin. When the 3.84 MHz
clock pulse is applied to TXCL, TXCO outputs a 384 kHz clock pulse, which is generated by
dividing the TXCL input by 10. The transmit data, synchronous to the 384 kHz clock pulse,
should be input to the TXD. In this case the devices do not use APLL, and the 3.84 MHz clock pulse
need not be continuous. (Refer to Fig. 1.)
TXCO
Transmit clock output.
When CRM0 - B6 is "0", TXCO outputs the 384 kHz clock pulse (APLL output) for monitoring
purposes. When CRM0 - B6 is "1", this pin outputs a 384 kHz clock pulse generated by dividing
the TXCI input by 10. (Refer to Fig. 1.)
TXW
Transmit data window signal input.
The transmit timing signal for the burst data is input to this pin. If TXW is "1", the modulation
data is output. (Refer to Fig. 1)
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¡ Semiconductor
(1) CRM0 – B6 = "0"
TXD
TXCI
(384 kHz)
TXW
TXCO
(384 kHz)
I, Q
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13
Delay of 6.25 symbols
(2) CRM0 – B6 = "1"
TXD
TXCI
(3.84 MHz)
TXW
TXCO
(3.84 kHz)
I, Q
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13
Delay of 6.25 symbols
Figure 1 Transmit Timing Diagram
,
,
MSM7586-01/03
D
n
-1 D
n
Ramp rise-up
2 symbols
Delay of 6.25 symbols
Ramp
Fall-down
2 symbols
D
n
-1 D
n
Ramp rise-up
2 symbols
Delay of 6.25 symbols
Ramp
Fall-down
2 symbols
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