ADVANCE
‡
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
REGISTEREDDDR
SDRAM DIMM
Features
• 184-pin, dual in-line memory module (DIMM)
• Fast data transfer rates PC1600, PC2100, or PC2700
• Utilizes 200 MT/s, 266 MT/s, and 333 MT/s DDR
SDRAM components
• Registered Inputs with one-clock delay
• Phase-lock loop (PLL) clock driver to reduce loading
• ECC, 1-bit error detection and correction
• 256MB (32 Meg x 72) and 512MB (64 Meg x 72)
• V
DD
= V
DD
Q = +2.5V
• V
DDSPD
= +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/received
with data—i.e., source-synchronous data capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 15.625µs (256MB), 7.8125µs (512MB) maximum
average periodic refresh interval
• Serial Presence Detect (SPD) with EEPROM
• Programmable READ CAS latency
MT18VDDF3272 – 256MB
MT18VDDF6472 – 512MB
For the latest data sheet, please refer to the Micron Web
site:
www.micron.com/moduleds
Figure 1: 184-Pin DIMM – MO-206
OPTIONS
MARKING
• Package
184-pin DIMM (gold)
• Frequency/CAS Latency
1
6ns/166MHz,(333MT/s)
7.5ns/133 MHz (266 MT/s)
7.5ns/133 MHz (266 MT/s)
7.5ns/133 MHz (266 MT/s)
10ns/100 MHz (200 MT/s)
NOTE:
G
CL = 2.5
CL = 2
CL = 2
CL = 2.5
CL = 2
-335
-262
-26A
-265
-202
1. Registered Mode will add one clock cycle to CL.
Table 1:
Address Table
256MB
512MB
4K
8K
Refresh Count
4K (A0–A11)
8K (A0–A12)
Row Addressing
4 (BA0, BA1)
4 (BA0, BA1)
Device Bank Addressing
32 Meg x 4
64 Meg x 4
Device Configuration
2K (A0–A9, A11) 2K (A0–A9, A11)
Column Addressing
1 (S0#)
1 (S0#)
Module Rank Addressing
32, 64 Meg x 72 DDR SDRAM DIMMs
DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
1
©2003 Micron Technology, Inc. All rights reserved.
‡
PRODUCTS
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
ADVANCE
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
Table 2:
Part Numbers and Timing Parameters
MODULE
DENSITY
256MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
256MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
CONFIGURATION
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
32 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
MODULE
BANDWIDTH
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
1.6 GB/s
1.6 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
1.6 GB/s
1.6 GB/s
MEMORY CLOCK/
DATA BIT RATE
6ns/333 MT/s
6ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
10ns/200 MT/s
10ns/200 MT/s
6ns/333 MT/s
6ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
10ns/200 MT/s
10ns/200 MT/s
LATENCY
(CL -
t
RCD -
t
RP)
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
2-2-2
2-2-2
PART NUMBER
MT18VDDF3272G-335__
MT18VDDF3272Y-335__
MT18VDDF3272G-26A__
MT18VDDF3272Y-26A__
MT18VDDF3272G-26A__
MT18VDDF3272Y-26A__
MT18VDDF3272G-265__
MT18VDDF3272Y-265__
MT18VDDF3272G-202__
MT18VDDF3272Y-202__
MT18VDDF6472G-335__
MT18VDDF6472Y-335__
MT18VDDF6472G-262__
MT18VDDF6472Y-262__
MT18VDDF6472G-26A__
MT18VDDF6472Y-26A__
MT18VDDF6472G-265__
MT18VDDF6472Y-265__
MT18VDDF6472G-202__
MT18VDDF6472Y-202__
NOTE:
All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for
current revision codes. Example: MT18VDDF3272G-265B1.
32, 64 Meg x 72 DDR SDRAM DIMMs
DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
ADVANCE
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
Table 3:
Pin Assignment
(184-Pin DIMM Front)
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
DQ17
DQS2
V
SS
A9
DQ18
A7
V
DD
Q
DQ19
A5
DQ24
V
SS
DQ25
DQS3
A4
V
DD
DQ26
DQ27
A2
V
SS
A1
CB0
CB1
V
DD
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
DQS8
A0
CB2
V
SS
CB3
BA1
DQ32
V
DD
Q
DQ33
DQS4
DQ34
V
SS
BA0
DQ35
DQ40
V
DD
Q
WE#
DQ41
CAS#
V
SS
DQS5
DQ42
DQ43
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
V
DD
NC
DQ48
DQ49
V
SS
NC
NC
V
DD
Q
DQS6
DQ50
DQ51
V
SS
NC
DQ56
DQ57
V
DD
DQS7
DQ58
DQ59
V
SS
NC
SDA
SCL
Table 4:
Pin Assignment
(184-Pin DIMM Back)
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
V
SS
DQ21
A11
DQS11
V
DD
DQ22
A8
DQ23
V
SS
A6
DQ28
DQ29
V
DD
Q
DQS12
A3
DQ30
V
SS
DQ31
CB4
CB5
V
DD
Q
CK0
CK0#
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
V
SS
DQS17
A10
CB6
V
DD
Q
CB7
V
SS
DQ36
DQ37
V
DD
DQS13
DQ38
DQ39
V
SS
DQ44
RAS#
DQ45
V
DD
Q
S0#
NC
DQS14
V
SS
DQ46
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
DQ47
NC
V
DD
Q
DQ52
DQ53
NC
V
DD
DQS15
DQ54
DQ55
V
DD
Q
NC
DQ60
DQ61
V
SS
DQS16
DQ62
DQ63
V
DD
Q
SA0
SA1
SA2
V
DDSPD
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
NOTE:
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
93
V
SS
94
DQ4
95
DQ5
96
V
DD
Q
97
DQS9
98
DQ6
99
DQ7
100
V
SS
101
NC
102
NC
103
NC
104 V
DD
Q
105 DQ12
106 DQ13
107 DQS10
108
V
DD
109 DQ14
110 DQ15
111
NC
112 V
DD
Q
113
NC
114 DQ20
115 NC/A12
V
REF
DQ0
V
SS
DQ1
DQS0
DQ2
V
DD
DQ3
NC
RESET#
V
SS
DQ8
DQ9
DQS1
V
DD
Q
NC
NC
V
SS
DQ10
DQ11
CKE0
V
DD
Q
DQ16
Pin 115 is a No Connect for 256MB modules, or A12 for 512MB modules.
Figure 2: Pin Locations
Front View
U6
U1
U2
U3
U4
U5
U7
U8
U9
U10
U11
PIN 1
PIN 52
PIN 53
PIN 92
Back View
U17
U12
U13
U14
U15
U16
U18
U19
U20
U21
U22
PIN 184
PIN 145
PIN 144
PIN 93
Indicates a V
DD
pin
Indicates a V
SS
pin
32, 64 Meg x 72 DDR SDRAM DIMMs
DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
ADVANCE
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
Table 5:
Pin Descriptions
SYMBOL
V
REF
WE#, CAS#, RAS#
CK0, CK0#
TYPE
Input
Input
DESCRIPTION
Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables for pin number and symbol information.
PIN NUMBERS
1
63, 65, 154
137, 138
21
CKE0
157
S0#
52, 59
BA0, BA1
27, 29, 32, 37, 41, 43, 48,
115
(
512MB
),
118, 122,
125, 130, 141
A0-A11
(256MB)
A0-A12
(512MB)
5, 14, 25, 36, 47, 56, 67,
78, 86, 97, 107, 119, 129,
140, 149, 159, 169, 177
44, 45, 49, 51, 134, 135,
142, 144
DQS0-DQS17
CB0-CB7
SSTL_2 reference voltage.
Command Inputs: RAS#, CAS#, and WE# (along with S0#) define
the command being entered.
Input Clock: CK, CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK,and negative edge of CK#. Output data (DQ and
DQS) is referenced to the crossings of CK and CK#.
Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all device banks idle), or ACTIVE POWER-DOWN
(row ACTIVE in any device bank).CKE is synchronous for POWER-
DOWN entry and exit, and for SELF REFRESH entry. CKE is
asynchronous for SELF REFRESH exit and for disabling the
outputs. CKE must be maintained HIGH throughout read and
write accesses. Input buffers (excluding CK, CK# and CKE) are
disabled during POWER-DOWN. Input buffers (excluding CKE)
are disabled during SELF REFRESH. CKE is an SSTL_2 input but
will detect an LVCMOS LOW level after V
DD
is applied.
Input Chip Selects: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of the
command code.
Input Bank Address: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Input Address Inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory
array in the respective device bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE
applies to one device bank (A10 LOW, device bank selected by
BA0, BA1) or all device banks (A10 HIGH). The address inputs
also provide the op-code during a MODE REGISTER SET
command. BA0 and BA1 define which mode register (mode
register or extended mode register) is loaded during the LOAD
MODE REGISTER command.
Input/ Data Strobe: Output with READ data, input with WRITE data.
Output DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
Input/ Check Bits: ECC, 1-bit error detection and correction.
Output
32, 64 Meg x 72 DDR SDRAM DIMMs
DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
ADVANCE
256MB, 512MB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
Table 5:
Pin Descriptions
SYMBOL
DQ0-DQ63
TYPE
Input/ Data I/Os: Data bus.
Output
DESCRIPTION
Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables for pin number and symbol information.
PIN NUMBERS
2, 4, 6, 8, 12,13, 19, 20,
23, 24, 28, 31, 33, 35, 39,
40, 53, 55, 57, 60, 61, 64,
68, 69, 72, 73, 79, 80, 83,
84, 87, 88, 94, 95, 98, 99,
105, 106, 109, 110, 114,
117, 121, 123, 126, 127,
131, 133, 146, 147, 150,
151, 153, 155, 161, 162,
165, 166, 170, 171, 174,
175, 178, 179
92
181, 182, 183
91
SCL
SA0-SA2
SDA
15, 22, 30, 54, 62, 77, 96,
104, 112, 128, 136, 143,
156, 164, 172, 180
7, 38, 46, 70, 85, 108,
120, 148, 168
3, 11, 18, 26, 34, 42, 50,
58, 66, 74, 81, 89, 93, 100,
116, 124, 132, 139, 145,
152, 160, 176
184
9, 16, 17, 71, 75, 76, 82,
90, 101, 102, 103, 111,
113, 115 (
256MB
),158,
163, 167, 173
V
DD
Q
Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Input Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to
Output transfer addresses and data into and out of the presence-detect
portion of the module.
Supply DQ Power Supply: +2.5V ±0.2V.
Input
V
DD
V
SS
Supply Power Supply: +2.5V ±0.2V.
Supply Ground.
V
DDSPD
NC
Supply Serial EEPROM positive power supply: +2.3V to +3.6V.
—
No Connect: These pins should be left unconnected.
32, 64 Meg x 72 DDR SDRAM DIMMs
DDF18C32_64x72G_B.fm - Rev. B 8/03 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
