256Mb: x4, x8, x16 SDRAM
Features
SDR SDRAM
MT48LC64M4A2 – 16 Meg x 4 x 4 banks
MT48LC32M8A2 – 8 Meg x 8 x 4 banks
MT48LC16M16A2 – 4 Meg x 16 x 4 banks
Features
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal, pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge
and auto refresh modes
• Self refresh mode (not available on AT devices)
• Auto refresh
– 64ms, 8192-cycle refresh (commercial and
industrial)
– 16ms, 8192-cycle refresh (automotive)
• LVTTL-compatible inputs and outputs
• Single 3.3V ±0.3V power supply
Options
– 60-ball TFBGA (x4, x8) (8mm x
16mm)
– 60-ball TFBGA (x4, x8) (8mm x
16mm) Pb-free
– 54-ball VFBGA (x16) (8mm x 14 mm)
– 54-ball VFBGA (x16) (8mm x 14 mm)
Pb-free
– 54-ball VFBGA (x16) (8mm x 8 mm)
– 54-ball VFBGA (x16) (8mm x 8 mm)
Pb-free
Timing – cycle time
– 6ns @ CL = 3 (x8, x16 only)
– 7.5ns @ CL = 3 (PC133)
– 7.5ns @ CL = 2 (PC133)
Self refresh
– Standard
– Low power
Operating temperature range
– Commercial (0˚C to +70˚C)
– Industrial (–40˚C to +85˚C)
– Automotive (–40˚C to +105˚C)
Revision
Notes:
1.
2.
3.
4.
Off-center parting line.
Only available on Revision D.
Only available on Revision G.
Contact Micron for availability.
Marking
FB
BB
FG
2
BG
2
F4
3
B4
3
•
-6A
-75
2
-7E
None
L
2
,
4
None
IT
AT
4
:D/:G
•
Options
• Configurations
– 64 Meg x 4 (16 Meg x 4 x 4 banks)
– 32 Meg x 8 (8 Meg x 8 x 4 banks)
– 16 Meg x 16 (4 Meg x 16 x 4 banks)
• Write recovery (
t
WR)
–
t
WR = 2 CLK
• Plastic package – OCPL
1
– 54-pin TSOP II OCPL
1
(400 mil)
(standard)
– 54-pin TSOP II OCPL
1
(400 mil)
Pb-free
Table 1: Key Timing Parameters
CL = CAS (READ) latency
Speed Grade
-6A
-75
-7E
Clock
Frequency (MHz)
167
133
133
Marking
64M4
32M8
16M16
A2
TG
P
•
•
Target
t
RCD-
t
RP-CL
3-3-3
3-3-3
2-2-2
t
RCD
(ns)
t
RP
(ns)
CL (ns)
18
20
15
18
20
15
18
20
15
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. W 05/15 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
1999 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
256Mb: x4, x8, x16 SDRAM
Features
Table 2: Address Table
Parameter
Configuration
Refresh count
Row addressing
Bank addressing
Column addressing
64 Meg x 4
16 Meg x 4 x 4 banks
8K
8K A[12:0]
4 BA[1:0]
2K A[9:0], A11
32 Meg x 8
8 Meg x 8 x 4 banks
8K
8K A[12:0]
4 BA[1:0]
1K A[9:0]
16 Meg x 16
4 Meg x 16 x 4 banks
8K
8K A[12:0]
4 BA[1:0]
512 A[8:0]
Table 3: 256Mb SDR Part Numbering
Part Numbers
MT48LC64M4A2TG
MT48LC64M4A2P
MT48LC64M4A2FB
1
MT48LC64M4A2BB
1
MT48LC32M8A2TG
MT48LC32M8A2P
MT48LC32M8A2FB
1
MT48LC32M8A2BB
1
MT48LC16M16A2TG
MT48LC16M16A2P
MT48LC16M16A2FG
MT48LC16M16A2BG
Note:
Architecture
64 Meg x 4
64 Meg x 4
64 Meg x 4
64 Meg x 4
32 Meg x 8
32 Meg x 8
32 Meg x 8
32 Meg x 8
16 Meg x 16
16 Meg x 16
16 Meg x 16
16 Meg x 16
Package
54-pin TSOP II
54-pin TSOP II
60-ball FBGA
60-ball FBGA
54-pin TSOP II
54-pin TSOP II
60-ball FBGA
60-ball FBGA
54-pin TSOP II
54-pin TSOP II
54-ball FBGA
54-ball FBGA
1. FBGA Device Decoder:
www.micron.com/decoder.
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. W 05/15 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
Features
Contents
General Description ......................................................................................................................................... 7
Automotive Temperature .............................................................................................................................. 7
Functional Block Diagrams ............................................................................................................................... 8
Pin and Ball Assignments and Descriptions ..................................................................................................... 11
Package Dimensions ....................................................................................................................................... 15
Temperature and Thermal Impedance ............................................................................................................ 19
Electrical Specifications .................................................................................................................................. 23
Electrical Specifications – I
DD
Parameters ........................................................................................................ 25
Electrical Specifications – AC Operating Conditions ......................................................................................... 27
Functional Description ................................................................................................................................... 30
Commands .................................................................................................................................................... 31
COMMAND INHIBIT .................................................................................................................................. 31
NO OPERATION (NOP) ............................................................................................................................... 32
LOAD MODE REGISTER (LMR) ................................................................................................................... 32
ACTIVE ...................................................................................................................................................... 32
READ ......................................................................................................................................................... 33
WRITE ....................................................................................................................................................... 34
PRECHARGE .............................................................................................................................................. 35
BURST TERMINATE ................................................................................................................................... 35
REFRESH ................................................................................................................................................... 36
AUTO REFRESH ..................................................................................................................................... 36
SELF REFRESH ....................................................................................................................................... 36
Truth Tables ................................................................................................................................................... 37
Initialization .................................................................................................................................................. 42
Mode Register ................................................................................................................................................ 44
Burst Length .............................................................................................................................................. 46
Burst Type .................................................................................................................................................. 46
CAS Latency ............................................................................................................................................... 48
Operating Mode ......................................................................................................................................... 48
Write Burst Mode ....................................................................................................................................... 48
Bank/Row Activation ...................................................................................................................................... 49
READ Operation ............................................................................................................................................. 50
WRITE Operation ........................................................................................................................................... 59
Burst Read/Single Write .............................................................................................................................. 66
PRECHARGE Operation .................................................................................................................................. 67
Auto Precharge ........................................................................................................................................... 67
AUTO REFRESH Operation ............................................................................................................................. 79
SELF REFRESH Operation ............................................................................................................................... 81
Power-Down .................................................................................................................................................. 83
Clock Suspend ............................................................................................................................................... 84
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. W 05/15 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
Features
List of Figures
Figure 1: 64 Meg x 4 Functional Block Diagram ................................................................................................. 8
Figure 2: 32 Meg x 8 Functional Block Diagram ................................................................................................. 9
Figure 3: 16 Meg x 16 Functional Block Diagram ............................................................................................. 10
Figure 4: 54-Pin TSOP (Top View) .................................................................................................................. 11
Figure 5: 60-Ball FBGA (Top View) ................................................................................................................. 12
Figure 6: 54-Ball VFBGA (Top View) ............................................................................................................... 13
Figure 7: 54-Pin Plastic TSOP "TG/P" (400 mil) ............................................................................................... 15
Figure 8: 60-Ball TFBGA "BB/FB" (8mm x 16mm) (x4, x8) ............................................................................... 16
Figure 9: 54-Ball VFBGA "BG/FG" (8mm x 14mm) (x16) .................................................................................. 17
Figure 10: 54-Ball VFBGA "B4/F4" (8mm x 8mm) (x16) ................................................................................... 18
Figure 11: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) ............................................... 21
Figure 12: Example: Temperature Test Point Location, 54-Ball VFBGA (Top View) ............................................ 21
Figure 13: Example: Temperature Test Point Location, 60-Ball FBGA (Top View) .............................................. 22
Figure 14: ACTIVE Command ........................................................................................................................ 32
Figure 15: READ Command ........................................................................................................................... 33
Figure 16: WRITE Command ......................................................................................................................... 34
Figure 17: PRECHARGE Command ................................................................................................................ 35
Figure 18: Initialize and Load Mode Register .................................................................................................. 43
Figure 19: Mode Register Definition ............................................................................................................... 45
Figure 20: CAS Latency .................................................................................................................................. 48
Figure 21: Example: Meeting
t
RCD (MIN) When 2 <
t
RCD (MIN)/
t
CK < 3 .......................................................... 49
Figure 22: Consecutive READ Bursts .............................................................................................................. 51
Figure 23: Random READ Accesses ................................................................................................................ 52
Figure 24: READ-to-WRITE ............................................................................................................................ 53
Figure 25: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 54
Figure 26: READ-to-PRECHARGE .................................................................................................................. 54
Figure 27: Terminating a READ Burst ............................................................................................................. 55
Figure 28: Alternating Bank Read Accesses ..................................................................................................... 56
Figure 29: READ Continuous Page Burst ......................................................................................................... 57
Figure 30: READ – DQM Operation ................................................................................................................ 58
Figure 31: WRITE Burst ................................................................................................................................. 59
Figure 32: WRITE-to-WRITE .......................................................................................................................... 60
Figure 33: Random WRITE Cycles .................................................................................................................. 61
Figure 34: WRITE-to-READ ............................................................................................................................ 61
Figure 35: WRITE-to-PRECHARGE ................................................................................................................. 62
Figure 36: Terminating a WRITE Burst ............................................................................................................ 63
Figure 37: Alternating Bank Write Accesses ..................................................................................................... 64
Figure 38: WRITE – Continuous Page Burst ..................................................................................................... 65
Figure 39: WRITE – DQM Operation ............................................................................................................... 66
Figure 40: READ With Auto Precharge Interrupted by a READ ......................................................................... 68
Figure 41: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 69
Figure 42: READ With Auto Precharge ............................................................................................................ 70
Figure 43: READ Without Auto Precharge ....................................................................................................... 71
Figure 44: Single READ With Auto Precharge .................................................................................................. 72
Figure 45: Single READ Without Auto Precharge ............................................................................................. 73
Figure 46: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 74
Figure 47: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 74
Figure 48: WRITE With Auto Precharge ........................................................................................................... 75
Figure 49: WRITE Without Auto Precharge ..................................................................................................... 76
Figure 50: Single WRITE With Auto Precharge ................................................................................................. 77
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. W 05/15 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
1999 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 SDRAM
Features
Figure 51:
Figure 52:
Figure 53:
Figure 54:
Figure 55:
Figure 56:
Figure 57:
Single WRITE Without Auto Precharge ............................................................................................
Auto Refresh Mode ........................................................................................................................
Self Refresh Mode ..........................................................................................................................
Power-Down Mode ........................................................................................................................
Clock Suspend During WRITE Burst ...............................................................................................
Clock Suspend During READ Burst .................................................................................................
Clock Suspend Mode .....................................................................................................................
78
80
82
83
84
85
86
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. W 05/15 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
1999 Micron Technology, Inc. All rights reserved.
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