256MB: (x72, SR) 244-Pin DDR2 Mini-RDIMM
Features
DDR2 SDRAM Mini-RDIMM
MT5HTF3272(P)K – 256MB
For component data sheets, refer to Micron’s Web site:
www.micron.com
Features
• 244-pin, mini-registered dual in-line memory
module (mini-RDIMM)
• Fast data transfer rates: PC-3200, PC2-4200, or
PC2-5300
• Supports ECC error detection and correction
• 256MB (32 Meg x 72)
• V
DD
= V
DD
Q = +1.8V
• V
DDSPD
= +1.7V to +3.6V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4n-bit prefetch architecture
• Single rank
• Multiple internal device banks for concurrent
operation
• Supports duplicate output strobe (RDQS/RDQS#)
• Programmable CAS# latency (CL)
• Posted CAS# additive latency (AL)
• WRITE latency = READ latency - 1
t
CK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
Figure 1:
244-Pin Mini-RDIMM (MO-244 R/C B)
Module height: 30.0mm (1.18in)
Options
Marking
• Parity
P
1
• Operating temperature
– Commercial (0°C
≤
T
A
≤ +70°C)
None
– Industrial (–40°C
≤
T
A
≤ +85°C)
I
• Package
– 244-pin mini-RDIMM (Pb-free)
Y
2
• Frequency/CAS latency
– 3.0ns @ CL = 5 (DDR2-667)
-667
– 3.75ns @ CL = 4 (DDR2-533)
-53E
– 5.0ns @ CL = 3 (DDR2-400)
-40E
• PCB height
– 30mm (1.18in)
Notes: 1. Contact Micron for industrial temperature
module offerings.
2. CL = CAS (READ) latency; registered mode
will add one clock cycle to CL.
Table 1:
Speed
Grade
-667
-53E
-40E
Key Timing Parameters
Data Rate (MT/s)
Industry Nomenclature
PC2-5300
PC2-4200
PC2-3200
CL = 5
667
–
–
CL = 4
533
533
400
CL = 3
400
400
400
t
RCD
t
RP
t
RC
(ns)
15
15
15
(ns)
15
15
15
(ns)
55
55
55
PDF: 09005aef818e3e75/Source: 09005aef818e3df5
htf5c32x72k.fm - Rev. B 2/07 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
256MB: (x72, SR) 244-Pin DDR2 Mini-RDIMM
Features
Table 2:
Addressing
256MB
Refresh count
Row addressing
Device bank addressing
Device page size per bank
Device configuration
Column addressing
Module rank addressing
8K
8K (A0–A12)
4 (BA0, BA1)
1KB
512Mb (32 Meg x 16)
1K (A0–A9)
1 (S0#)
Table 3:
Part Numbers and Timing Parameters – 256MB
Base device: MT47H32M16
1
, 512Mb DDR2 SDRAM
Module
Density
256MB
256MB
256MB
Module
Bandwidth
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Latency
(CL-
t
RCD-
t
RP)
5-5-5
4-4-4
3-3-3
Part Number
2
MT5HTF3272(P)KY-667__
MT5HTF3272(P)KY-53E__
MT5HTF3272(P)KY-40E__
Notes:
Configuration
32 Meg x 72
32 Meg x 72
32 Meg x 72
1. Data sheets for the base devices can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown), designating component and PCB
revisions. Consult factory for current revision codes. Example: MT5HTF3272KY-40ED1.
PDF: 09005aef818e3e75/Source: 09005aef818e3df5
htf5c32x72k.fm - Rev. B 2/07 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
256MB: (x72, SR) 244-Pin DDR2 Mini-RDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 4:
Pin Assignments
244-Pin Mini-RDIMM Front
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
RESET#
NC
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
DQ19
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1
57
58
59
60
61
62
V
SS
DQ24
DQ25
V
SS
DQS3#
DQS3
V
SS
DQ26
DQ27
V
SS
CB0
CB1
V
SS
DQS8#
DQS8
V
SS
CB2
CB3
V
SS
NC
V
DD
Q
CKE0
V
DD
NC
NC/
E
RR
_O
UT
V
DD
Q
A11
A7
V
DD
A5
A4
Notes:
63
64
65
66
67
68
2
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
V
DD
Q
A2
V
DD
V
SS
V
SS
NC/
P
AR
_I
N
V
DD
A10
BA0
V
DD
WE#
V
DD
Q
CAS#
V
DD
Q
NC
NC
V
DD
Q
NC
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
DQS5#
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
SA2
NC
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7#
DQS7
V
SS
DQ58
DQ59
V
SS
SA0
SA1
244-Pin Mini-RDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
V
SS
DQ4
DQ5
V
SS
DM0
NC
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
NC
V
SS
RFU
RFU
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2
NC
V
SS
DQ22
DQ23
V
SS
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
DQ28
DQ29
V
SS
DM3
NC
V
SS
DQ30
DQ31
V
SS
CB4
CB5
V
SS
DM8
NC
V
SS
CB6
CB7
V
SS
NC
V
DD
Q
NC
V
DD
NC
NC
V
DD
Q
A12
A9
V
DD
A8
A6
V
DD
Q
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
A3
A1
V
DD
CK0
CK0#
V
DD
A0
BA1
V
DD
RAS#
V
DD
Q
S0#
V
DD
Q
ODT0
NC
V
DD
NC
V
SS
DQ36
DQ37
V
SS
DM4
NC
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
DM5
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
NC
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
RFU
RFU
V
SS
DM6
NC
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7
NC
V
SS
DQ62
DQ63
V
SS
SDA
SCL
V
DDSPD
1. Pin 56 is NC for non-parity and E
RR
_O
UT
and parity.
2. Pin 68 is NC for non-parity and P
AR
_I
N
for parity.
PDF: 09005aef818e3e75/Source: 09005aef818e3df5
htf5c32x72k.fm - Rev. B 2/07 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
256MB: (x72, SR) 244-Pin DDR2 Mini-RDIMM
Pin Assignments and Descriptions
Table 5:
Symbol
ODT0
Pin Descriptions
Type
Description
Input
On-die termination:
ODT (registered HIGH) enables termination resistance internal to the
(SSTL_18) DDR2 SDRAM. When enabled, ODT is only applied to each of the following pins: DQ, DQS,
DQS#, RDQS, RDQS#, CB, and DM. The ODT input will be ignored if disabled via the LOAD
MODE (LM) command.
CK0, CK0#
Input
Clock:
CK and CK# are differential clock inputs. All address and control input signals are
(SSTL_18) sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data
(DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.
CKE0
Input
Clock enable:
CKE (registered HIGH) activates and CKE (registered LOW) deactivates
(SSTL_18) clocking circuitry on the DDR2 SDRAM.
S0#
Input
Chip select:
S# enables (registered LOW) and disables (registered HIGH) the command
(SSTL_18) decoder. All commands are masked when S# is registered HIGH. S# provides for external
rank selection on systems with multiple ranks. S# is considered part of the command code.
RAS#, CAS#, WE#
Input
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being
(SSTL_18) entered.
BA0, BA1
Input
Bank address inputs:
BA0–BA1 define to which device bank an ACTIVE, READ, WRITE, or
(SSTL_18) PRECHARGE command is being applied. BA0–BA1 define which mode register, including
MR, EMR, EMR(2), or EMR(3), is loaded during the LM command.
A0–A12
Input
Address inputs:
Provide the row address for ACTIVE commands and the column address
(SSTL_18) and auto precharge bit (A10) for READ/WRITE commands to select one location out of the
memory array in the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0–BA1) or all device banks (A10 HIGH). The address inputs also provide the
op-code during an LM command.
Input
P
AR
_I
N
Parity bit for the address and control bus.
(SSTL_18)
SCL
Input
Serial clock for presence-detect:
SCL is used to synchronize the presence-detect data
(SSTL_18) transfer to and from the module.
SA0–SA2
Input
Presence-detect address inputs:
These pins are used to configure the presence-detect
(SSTL_18) device.
RESET#
Input
Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can be
(SSTL_18) used during power-up to ensure that CKE is LOW and DQs are High-Z.
DQ0–DQ63
I/O
Data input/output:
Bidirectional data bus.
(SSTL_18)
DQS0–DQS8,
I/O
Data strobe:
Output with read data, input with write data for source synchronous
DQS0#–DQS8# (SSTL_18) operation. Edge-aligned with read data, center-aligned with write data. DQS# is only used
when differential data strobe mode is enabled via the LM command. DQS9#–DQS17# are
only used when RDQS# is enabled via the LM command.
DM0–DM8
I/O
Input data mask:
DM is an input mask signal for write data. Input data is masked when
(SSTL_18) DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on
both edges of DQS. Although DM pins are input-only, the DM loading is designed to match
that of DQ and DQS pins. If RDQS is enabled, DQS9#–DQS17# are used only during the READ
command.
CB0–CB7
I/O
Check bits.
(SSTL_18)
SDA
I/O
Serial presence-detect data:
SDA is a bidirectional pin used to transfer addresses and
(SSTL_18) data into and out of the presence-detect portion of the module.
Output Parity error found on the address and control bus.
E
RR
_O
UT
(open
drain)
Supply
Power supply:
1.8V ±0.1V.
V
DD
/V
DD
Q
Supply SSTL_18 reference voltage.
V
REF
PDF: 09005aef818e3e75/Source: 09005aef818e3df5
htf5c32x72k.fm - Rev. B 2/07 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
256MB: (x72, SR) 244-Pin DDR2 Mini-RDIMM
Pin Assignments and Descriptions
Table 5:
Symbol
V
SS
V
DDSPD
NC
RFU
Pin Descriptions (continued)
Type
Supply
Supply
–
–
Description
Ground.
Serial EEPROM positive power supply:
+1.7V to +3.6V.
No connect:
These pins should be left unconnected.
Reserved for future use.
PDF: 09005aef818e3e75/Source: 09005aef818e3df5
htf5c32x72k.fm - Rev. B 2/07 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
DSP 与 ARM 处理器
