ADVANCE
‡
HARMONY 1Mb and 2Mb TCAMs
HARMONY
Data Sheet
FEATURES
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16K and 8K x 136-bit full TCAMs
Configurable as 8K/4K x 272 or 32K/16K x 68
68-bit interface operates at 13.6 Gb/s
Sustains 100 million searches per second on a
34-bit, 68-bit, or 136-bit field
Performs 50 million searches per second in 272-bit
configuration
Holds multiple word widths within the same device
Provides synchronous pipelined operation
Cascades up to 31 TCAMs without performance
degradation or additional logic
Allows glueless interface to industry-standard
synchronous SRAMs
Supports IEEE 1149.1 JTAG Test Access
1.8V and 3.3V power supply
272-ball HSBGA package
1Mb: MT75W8Y136HBB
2Mb: MT75W16Y136HBB
For the latest data sheet, please refer to the Micron Web site:
www.micron.com/datasheets
GENERAL DESCRIPTION
The Micron
®
Harmony device is a high-performance,
pipelined, synchronous, ternary content addressable
memory (TCAM) device, which is available in two
configurations:
• 1Mb version, organized as 8K x 136 bits
• 2Mb version, organized as 16K x 136 bits
Additionally, the organization is flexible; the 2Mb
Harmony device can be reconfigured as 32K x 68 bits or
8K x 272 bits, and the 1Mb Harmony device can be
reconfigured as 16K x 68 bits or 4K x 272 bits.
Harmony sustains 100 million searches per second
when organized as 136 bit wide or 68 bit wide, and 50
million searches per second when organized as 272 bit
wide. Harmony also supports a search table of 34 bits
with the help of the global mask registers (GMRs).
This high-speed device can be used in a variety of
networking and communications applications, such as
longest-prefix match (CIDR), MPLS, and Layer 2, 3, and
4 protocols.
The flexibility of the Harmony device allows the use
of multiple search tables within the same device. It
simultaneously compares data against an entire pre-
stored array of addresses, providing a performance
advantage by reducing search times an order-of-
magnitude over typical binary or tree-based search
algorithms. This Harmony device can be designed into
many applications, but it is particularly well suited to
performing highly intensive search operations.
Figure 1. Harmony Block Diagram
TRST#
TCLK
TMS
TDI
TDO
CSO[1:0]
CSI[6:0]
BHO[2:0]
BHI[2:0]
UID[4:0]
MF
MM#
MV
FF
FI[6:0]
FO[1:0]
High-Speed
Interface
SADR[21:0]
OE#
WE#
CE#
ALE#
SCLK
Harmony 1Mb and 2Mb TCAMs
Harmony Data Sheet.fm - Rev. 9/02
SEN[3:0]
HARMONY
Cascade
CLK
PHASE#
RST#
Controller
ACK#
EOT
OP[8:0]
OPV
DQ[67:0]
SRAM
Interface
JTAG
1
©2002, Micron Technology Inc.
‡
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
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HARMONY 1Mb and 2Mb TCAMs
TABLE OF CONTENTS
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . 1
Functional Description . . . . . . . . . . . . . . . . . . . 3
Address and Data Bus . . . . . . . . . . . . . . . . . . . . 3
Data Bus DQ[67:0] . . . . . . . . . . . . . . . . . . . . . . . 3
Instruction Bus . . . . . . . . . . . . . . . . . . . . . . . . . . 3
SRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Cascading Harmony Devices . . . . . . . . . . . . . . 3
Dual Data Rate Clock . . . . . . . . . . . . . . . . . . . . . 4
Power Management . . . . . . . . . . . . . . . . . . . . . . 4
Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . 4
JTAG Interface and Test Access Port . . . . . . . 5
Harmony Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
TCAM Architecture . . . . . . . . . . . . . . . . . . . . . . . . 10
Content Addressable Memory . . . . . . . . . . . . 10
Data Path Description . . . . . . . . . . . . . . . . . . . 10
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . 12
Comparand Registers . . . . . . . . . . . . . . . . . . . 12
Global Mask Registers . . . . . . . . . . . . . . . . . . . 13
Result Registers . . . . . . . . . . . . . . . . . . . . . . . . . 14
Instruction Register . . . . . . . . . . . . . . . . . . . . . 15
Information Register . . . . . . . . . . . . . . . . . . . . 15
Burst Read Address Register. . . . . . . . . . . . . . 16
Burst Write Address Register . . . . . . . . . . . . . 16
Next Free Address Register. . . . . . . . . . . . . . .
Configuration Register . . . . . . . . . . . . . . . . . .
Harmony Instructions . . . . . . . . . . . . . . . . . . . . .
Instruction Codes. . . . . . . . . . . . . . . . . . . . . . .
Instructions And Instruction Parameters . .
SEARCH Instructions. . . . . . . . . . . . . . . . . . . .
SRAM Addressing . . . . . . . . . . . . . . . . . . . . . . .
Application Information . . . . . . . . . . . . . . . . . . .
Depth Cascading . . . . . . . . . . . . . . . . . . . . . . .
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Sequencing . . . . . . . . . . . . . . .
32-bit Search Applications . . . . . . . . . . . . . . .
Test Access Port . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Specifications . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings. . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . .
DC Electrical Characteristics . . . . . . . . . . . . .
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HSBG Thermal Resistance . . . . . . . . . . . . . . .
AC Timing Waveforms. . . . . . . . . . . . . . . . . . . . .
Packaging information . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . .
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . .
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Harmony 1Mb and 2Mb TCAMs
Harmony Data Sheet.fm - Rev 9/02
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©2002, Micron Technology Inc.
ADVANCE
HARMONY 1Mb and 2Mb TCAMs
FUNCTIONAL DESCRIPTION
The Harmony Block Diagram (Figure 1) consists of
the following components: TCAM, high-speed I/O
interface, cascade control, SRAM interface, test assess
port, and the instruction and DQ bus interface. Figure 2
illustrates how Harmony is typically connected to other
devices in a system.
instruction and the related parameters are listed in
“Harmony Instructions” on page 17.
Each instruction execution requires two clock
cycles, but the bidirectional DQ[67:0] bus runs every
cycle, providing a simple double data rate I/O. A second
port provides the address and control lines necessary to
drive an external SRAM. SEARCH operations drive the
resulting match address on the SRAM address lines,
allowing associated data to be stored in the external
SRAM rather than the internal device memory. READ
and WRITE operations also drive the SRAM address
lines with the address of the TCAM word being read or
written.
SRAM INTERFACE
The SRAM interface section drives the ADDRESS
and CONTROL signals required to access the external
SRAM. Harmony can generate a synchronous output
clock (SCLK) to perform SRAM accesses. Using the
SCLK signal, Harmony reduces the amount of required
interface logic by synchronously driving the SRAM
ADDRESS and CONTROL signals. When cascaded, the
Harmony device, which contains a match in its results
register, drives the SRAM bus. However, when no
match exists, the last Harmony device of the cascade
(LRAM = 1) drives the SRAM bus. Also, when cascaded,
this section inserts pipeline delays for the SRAM
address and SRAM control for Harmony. The SRAM
data bus is connected to the appropriate host ASIC;
therefore, SRAM data does not pass through Harmony.
SRAM Addressing
The SRAM address consists of information obtained
from the DQ bus and either the lowest match address
from a SEARCH instruction or the address supplied by
the Instruction Register. The interface timing and
control selects the address from the Instruction Register
by asserting the applicable READ or WRITE instruction.
During a READ or WRITE instruction to the SRAM, if the
identification (UID) is the global address, then the last
TCAM on the SRAM bus of the depth-cascaded devices
drives the SRAM signals (LCAM = 1).
CASCADING HARMONY DEVICES
Harmony devices can be cascaded to provide addi-
tional depth. Up to 31 devices can be cascaded without
any performance degradation. Harmony performs the
necessary arbitration to determine which of the
cascaded devices drives the SRAM bus, thereby elimi-
nating bus contention. Each device in the cascade is
assigned a unique ID number, which helps identify the
device that has found the match.
Figure 2. Typical Harmony Connections
ASIC
CAM Control Bus
(12 or 16 bit)
CAM Address/
Data Bus (68 bit)
CAM Status Bus
(4 bit)
Harmony
SRAM Address/
Control Bus (26 bit)
SRAM
Harmony has four major buses that interface with
other devices: the TCAM address/data bus, the TCAM
control bus, the TCAM status bus, and the SRAM
address/control bus. Other interfaces include a cascade
interface that is used when multiple Harmony chips are
cascaded to increase the table size and a JTAG interface.
ADDRESS AND DATA BUS
The TCAM address/data bus is a 68-bit bidirectional
bus that performs one I/O operation per clock cycle.
Note:
TCAM operations require two or four clock
cycles each, so if the system clock is 200 MHz,
an I/O operation is performed every 5ns.
However, each TCAM operation requires 10
or 20ns for completion, depending on the
operation.
DATA BUS DQ[67:0]
The Data Bus DQ[67:0] is used for data transfer to
and from the TCAM array, which comprise data and
mask arrays. The DQ bus transports the search data
during the SEARCH operation. The DQ bus also trans-
ports addressing and data during the READ/WRITE
operations of the TCAM array and the internal registers.
Additionally, the DQ bus carries the address infor-
mation for the SRAM bus.
INSTRUCTION BUS
The instruction bus OP[8:0] carries the instruction
and its associated parameters. The description of each
Harmony 1Mb and 2Mb TCAMs
Harmony Data Sheet.fm - Rev 9/02
SRAM Data Bus
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©2002, Micron Technology Inc.
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HARMONY 1Mb and 2Mb TCAMs
Cascade Control
The cascade control section drives the CASCADE
OUTPUT (CSO) signal when the Harmony devices are
depth cascaded. Harmony also contains the control
logic to determine if the entry in a single device is full or
if the table consisting of multiple devices is full. In
addition, the cascade control section provides support
for multiple matches. Although the cascade control
section does not drive the validity of matches, the
success of matches, multiple matches, or the required
SRAM signals (these signals are located in the controller
section of the block diagram), it does contain the
control logic to enable the output for these signals.
The diagram showing the cascading of eight devices
is shown in Figure 23 on page 34.
Cascading CSO[1:0] and CSI[6:0] Signals
With eight devices cascaded, the search table can be
either 128K x 136 bits, 256K x 68 bits, or 64K x 272 bits
wide. Figure 23 on page 34 shows the pin connections
between the cascaded Harmony devices.
Each Harmony device asserts the CASCADE OUT
signals CSO[0] and CSO[1] to inform the downstream
devices of the result. The CASCADE IN signals CSI[6:0]
for a device are connected to the CSO signals of the
upstream devices.
Note:
The host ASIC must program the table size
TLSZ[3:2] bits in the Instruction Register to
“01” for each of the devices in a cascade, as
described in Figure 7 on page 12.
136-bit data words. Furthermore, Harmony can
perform consecutive searches on 136-bit data words.
The PHASE# signal ensures that these double-speed
operations are correctly aligned with Harmony.
Master Clock (CLK)
Harmony receives the master clock CLK, which has a
maximum frequency of 200 MHz.
PHASE# Signal
The PHASE# signal runs at half the frequency of the
master clock and generates the internal clock (see
Figure 3). The Harmony uses this divided clock for
internal operations.
SRAM Clock (SCLK)
The SCLK is an output clock and is generated for the
SRAM bus. Because this clock is generated from the
internal clock, it allows users to perform the SRAM
READ and WRITE operations synchronous to the
Harmony device.
Figure 3. Relationship Between CLK,
PHASE#, and SCLK Signals
A
CLK
B
A
B
A
B
PHASE#
Depth Cascading for a FULL Signal
FULL OUT FO[0] and FO[1] are the same logical
signal. When eight Harmony devices are cascaded, one
of these FULL signals must be connected to the FI
signals of up to four downstream devices. Bit[0] of each
of the 68-bit entries indicates if the entry in the data
array is empty or occupied. The “Write To Next Free
Address” instruction uses this information.
Each signal of the FI[6:0] bus is connected to the
FO[0] or FO[1] output of the upstream cascaded device,
to generate the FULL FLAG FF. Figure 24 on page 35
shows the interconnections of these signals between the
cascaded devices.
DUAL DATA RATE CLOCK
The dual data rate clock, configured as cycle A and
cycle B, allows the DQ bus interface to operate at double
speed while maintaining 100 MHz search rates even
though the I/O width is less than the data width. Hence,
only 68 pins, instead of 136 pins, are required to support
SCLK
POWER MANAGEMENT
The power management feature within Harmony
reduces power dissipation by limiting SEARCH opera-
tions to selected portions of the TCAM. Predetermined
portions of data can be selected and isolated for a
SEARCH instruction. The input pins (SEN[3:0]) inde-
pendently control four equal sections of the device. To
disable power management, set bit 0 of the Configu-
ration Register or connect SEN[3:0] to V
SS
.
RESET FUNCTION
Hardware Reset
RST# is the reset pin on Harmony. Driving this pin
LOW performs a hardware reset and initializes the
Harmony device to a known state.
Harmony 1Mb and 2Mb TCAMs
Harmony Data Sheet.fm - Rev 9/02
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©2002, Micron Technology Inc.
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HARMONY 1Mb and 2Mb TCAMs
Software Reset
Bit[0] in the Instruction Register and the reset pin
work in a similar way. When Bit[0] is set to “1,” it
generates an internal reset pulse lasting for eight clock
cycles and then automatically resets to “0.”
Please refer to the Micron Application Note: “Initial-
ization of Harmony TCAM.”
JTAG INTERFACE AND TEST ACCESS PORT
The Harmony test access port provides an interface
for manufacturing tests and consists of the boundary
scan access port used to support the standard JTAG
IEEE 1149.1. See page 6 for more details on JTAG
interface and test access port.
HARMONY SIGNALS
Table 1: Harmony Signal Nomenclature
SYMBOL
TYPE DESCRIPTION
CLOCKS AND RESET
CLK
PHASE#
SCLK
RST#
I
I
T
1
Master Clock.
Harmony samples all the control and data signals either on the positive edge of CLK, or on the positive
of CLK when PHASE# is LOW.
PHASE#.
This signal runs at half the frequency of CLK and generates an internal clock from CLK.
SRAM Clock.
This signal is the clock for the external SRAM bus. It runs at half the speed of the input CLK, going LOW
on the CLK positive edge that PHASE# is HIGH. The SRAM clock must be enabled by the SCE bit in the Configuration
Register.
Reset.
Driving RST# LOW initializes the device to a known state.
I
INSTRUCTION AND DQ BUS
Instruction Bus.
OP[1:0] specifies the instruction. OP[8:2] contains the instruction parameters. The descriptions of
individual instructions explain the details of the parameters. The encoding of instructions based on the [1:0] fields are:
00:READ
01:WRITE
10:SEARCH
11:WRITE NEXT FREE ADDRESS
Op-Code Valid.
OPV qualifies the instruction bus.
0:No Instruction, 1:Instruction
Address/Data Bus.
DQ[67:0] carries the read and write address and data during REGISTER, DATA, and MASK ARRAY
operations. It carries the compare data during SEARCH operations. It also carries TCAM array, SRAM, or regular address
during READ and WRITE operations.
Read Acknowledge.
ACK indicates that valid data is available on the DQ bus during REGISTER, DATA WORD, AND
WORD MASK ARRAY READ operations, or the data is available on the SRAM data bus during operations.
End of Transfer.
EOT indicates the end of burst transfer during READ or WRITE burst operations.
Match Flag.
When asserted, MF indicates that the device is selected in a SEARCH operation. MM# must be enabled by
the MME bit in the Configuration Register.
Match Flag Valid.
When asserted, MV qualifies the match flag and multi-match flag signals.
Multi-Match Flag.
When asserted, indicates that two or more matches were found. MM# must be enabled by the MME
bit in the Configuration Register. MM# may be left unconnected, but if used it should be connected to V
DDQ
with a
10KΩ resister.
Search Enable.
SEN[3:0] controls which pages within the TCAM array participate in SEARCH operations. These pins
have pull-down resistors, so they may be left unconnected. They must be enabled by the SENE bit in the Configuration
Register.
OP[8:0]
I
OPV
I
DQ[67:0]
I/O
T
1
T
1
T
1
T
1
T
1
ACK
EOT
MF
MV
MM#
SEN[3:0]
I
SRAM INTERFACE
SADR[21:0]
CE#
WE#
OE#
ALE#
T
1
T
1
T
1
T
1
T
1
SRAM Address.
SADR contains address lines to access external SRAMs that contains associative data. See Table 26 and
Table 27 on page 32 for SRAM bus addressing details.
SRAM Chip Enable.
CE# is the chip enable control for external SRAMs.
SRAM Write Enable.
WE# is the write enable control for external SRAMs.
SRAM Output Enable.
OE# is the output enable control for external SRAMs.
Address Latch Enable.
ALE# is the latch enable control for external SRAMs.
Harmony 1Mb and 2Mb TCAMs
Harmony Data Sheet.fm - Rev 9/02
5
©2002, Micron Technology Inc.
