MT88L70
3 Volt Integrated DTMF Receiver
Data Sheet
Features
•
•
•
•
•
•
•
•
•
2.7 - 3.6 volt operation
Complete DTMF receiver
Low power consumption
Internal gain setting amplifier
Adjustable guard time
Central office quality
Power-down mode
Inhibit mode
Functionally compatible with Zarlink’s MT8870D
Ordering Information
MT88L70AE
MT88L70AS
MT88L70AN
MT88L70ASR
MT88L70ANR
MT88L70AE1
MT88L70AN1
MT88L70ANR1
MT88L70AS1
MT88L70ASR1
18
18
20
18
20
18
20
20
18
18
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
PDIP
SOIC
SSOP
SOIC
SSOP
PDIP*
SSOP*
SSOP*
SOIC*
SOIC*
Tubes
Tubes
Tubes
Tape &
Tape &
Tubes
Tubes
Tape &
Tubes
Tape &
August 2005
Reel
Reel
Reel
Reel
* Pb Free Matte Tin
-40°C to +85°C
Applications
•
•
•
•
•
•
Paging systems
Repeater systems/mobile radio
Credit card systems
Remote control
Personal computers
Telephone answering machine
VDD
VSS
VRef
Description
The MT88L70 is a complete 3 Volt, DTMF receiver
integrating both the bandsplit filter and digital decoder
functions. The filter section uses switched capacitor
techniques for high and low group filters; the decoder
uses digital counting techniques to detect and decode
all 16 DTMF tone-pairs into a 4-bit code. External
component count is minimized by on chip provision of
a differential input amplifier, clock oscillator and latched
three-state bus interface.
INH
PWDN
Bias
Circuit
VRef
Buffer
Q1
High Group
Filter
Dial
Tone
Filter
Low Group
Filter
Zero Crossing
Detectors
Digital
Detection
Algorithm
Code
Converter
and Latch
Q2
Q3
Q4
Chip Chip
Power Bias
IN +
IN -
GS
to all
Chip
Clocks
St
GT
Steering
Logic
OSC1
OSC2
St/GT
ESt
STD
TOE
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved.
MT88L70
Data Sheet
IN+
IN-
GS
VRef
INH
PWDN
OSC1
OSC2
VSS
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
VDD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE
IN+
IN-
GS
VRef
INH
PWDN
NC
OSC1
OSC2
VSS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
St/GT
ESt
StD
NC
Q4
Q3
Q2
Q1
TOE
18 PIN PDIP/SOIC
20 PIN SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
18
1
2
3
4
5
6
7
8
9
10
11-
14
15
20
1
2
3
4
5
6
8
9
10
11
12-
15
17
Name
IN+
IN-
GS
V
Ref
INH
Non-Inverting Op-Amp (Input).
Inverting Op-Amp (Input).
Gain Select.
Gives access to output of front end differential amplifier for connection of
feedback resistor.
Reference Voltage (Output).
Nominally V
DD
/2 is used to bias inputs at mid-rail (see Figure 5
and Figure 6).
Inhibit (Input).
Logic high inhibits the detection of tones representing characters A, B, C and
D. This pin input is internally pulled down.
Description
PWDN
Power Down (Input).
Active high. Powers down the device and inhibits the oscillator. This
pin input is internally pulled down.
OSC1
OSC2
V
SS
TOE
Clock (Input).
Clock (Output).
A 3.579545 MHz crystal connected between pins OSC1 and OSC2
completes the internal oscillator circuit.
Ground (Input).
0 V typical.
Three State Output Enable (Input).
Logic high enables the outputs Q1-Q4. This pin is pulled
up internally.
Q1-Q4
Three State Data (Output).
When enabled by TOE, provide the code corresponding to the
last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high
impedance.
StD
Delayed Steering (Output).Presents
a logic high when a received tone-pair has been
registered and the output latch updated; returns to logic low when the voltage on St/GT falls
below V
TSt
.
Early Steering (Output).
Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to
a logic low.
16
18
ESt
2
Zarlink Semiconductor Inc.
MT88L70
Pin Description
Pin #
18
17
20
19
Name
St/GT
Description
Data Sheet
Steering Input/Guard time (Output) Bidirectional.
A voltage greater than V
TSt
detected at
St causes the device to register the detected tone pair and update the output latch. A voltage
less than V
TSt
frees the device to accept a new tone pair. The GT output acts to reset the
external steering time-constant; its state is a function of ESt and the voltage on St.
Positive power supply (Input).
+3 V typical.
No Connection.
18
20
7, 16
V
DD
NC
Functional Description
The MT88L70 monolithic DTMF receiver offers small size, low power consumption and high performance, with 3
volt operation. Its architecture consists of a bandsplit filter section, which separates the high and low group tones,
followed by a digital counting section which verifies the frequency and duration of the received tones before passing
the corresponding code to the output bus.
Filter Section
Separation of the low-group and high group tones is achieved by applying the DTMF signal to the inputs of two
sixth-order switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group
frequencies. The filter section also incorporates notches at 350 and 440 Hz for exceptional dial tone rejection. Each
filter output is followed by a single order switched capacitor filter section which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of
unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the
incoming DTMF signals.
Decoder Section
Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the
incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm
protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency
deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the
detector recognizes the presence of two valid tones (this is referred to as the “signal condition” in some industry
specifications) the “Early Steering” (ESt) output will go to an active state. Any subsequent loss of signal condition
will cause ESt to assume an inactive state (see “Steering Circuit”).
Steering Circuit
Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character
recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt
causes v
c
(see Figure 3) to rise as the capacitor discharges. Provided signal condition is maintained (ESt remains
high) for the validation period (t
GTP
), v
c
reaches the threshold (V
TSt
) of the steering logic to register the tone pair,
latching its corresponding 4-bit code (see Table 1) into the output latch. At this point the GT output is activated and
drives v
c
to V
DD
. GT continues to drive high as long as ESt remains high. Finally, after a short delay to allow the
output latch to settle, the delayed steering output flag (StD) goes high, signalling that a received tone pair has been
registered. The contents of the output latch are made available on the 4-bit output bus by raising the three state
control input (TOE) to a logic high. The steering circuit works in reverse to validate the interdigit pause between
signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal
interruptions (dropout) too short to be considered a valid pause. This facility, together with the capability of selecting
3
Zarlink Semiconductor Inc.
MT88L70
Data Sheet
the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system
requirements.
Digit
ANY
1
2
3
4
5
6
7
8
9
0
*
#
A
B
C
D
A
B
C
D
TOE
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
INH
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
H
H
H
H
ESt
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
Q
4
Z
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
Q
3
Z
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
Q
2
Z
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
Q
1
Z
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
undetected, the output code
will remain the same as the
previous detected code
Table 1 - Functional Decode Table
L=LOGIC LOW, H=LOGIC HIGH, Z=HIGH IMPEDANCE
X = DON‘T CARE
Guard Time Adjustment
In many situations not requiring selection of tone duration and interdigital pause, the simple steering circuit shown
in Figure 3 is applicable. Component values are chosen according to the formula:
t
REC
=t
DP
+t
GTP
t
ID
=t
DA
+t
GTA
The value of t
DP
is a device parameter (see Figure 7) and t
REC
is the minimum signal duration to be recognized by
the receiver. A value for C of 0.1
µF
is recommended for most applications, leaving R to be selected by the
designer.
4
Zarlink Semiconductor Inc.
MT88L70
V
DD
Data Sheet
V
DD
St/GT
ESt
R
StD
MT88L70
C
v
c
t
GTA
=(RC)In(V
DD
/V
TSt
)
t
GTP
=(RC)In[V
DD
/(V
DD
-V
TSt
)]
Figure 3 - Basic Steering Circuit
Different steering arrangements may be used to select independently the guard times for tone present (t
GTP
) and
tone absent (t
GTA
). This may be necessary to meet system specifications which place both accept and reject limits
on both tone duration and interdigital pause. Guard time adjustment also allows the designer to tailor system
parameters such as talk off and noise immunity. Increasing t
REC
improves talk-off performance since it reduces the
probability that tones simulated by speech will maintain signal condition long enough to be registered. Alternatively,
a relatively short t
REC
with a long t
DO
would be appropriate for extremely noisy environments where fast acquisition
time and immunity to tone drop-outs are required. Design information for guard time adjustment is shown in Figure
4.
Power-down and Inhibit Mode
A logic high applied to pin 6 (PWDN) will power down the device to minimize the power consumption in a standby
mode. It stops the oscillator and the functions of the filters.
Inhibit mode is enabled by a logic high input to the pin 5 (INH). It inhibits the detection of tones representing
characters A, B, C, and D. The output code will remain the same as the previous detected code (see Table 1).
V
DD
C
1
St/GT
t
GTP
=(R
P
C
1
) In [V
DD
/ (V
DD
-V
TSt
)]
t
GTA
=(R
1
C
1
) In (V
DD
/ V
TSt
)
R
P
= (R
1
R
2
) / (R
1
+ R
2
)
R
1
ESt
R
2
a) decreasing t
GTP
; (t
GTP
< t
GTA
)
t
GTP
=(R
1
C
1
) In [V
DD
/ (V
DD
-V
TSt
)]
V
DD
C
1
St/GT
t
GTA
=(R
P
C
1
) In (V
DD
/ V
TSt
)
R
P
= (R
1
R
2
) / (R
1
+ R
2
)
R
1
ESt
R
2
b) decreasing t
GTA
; (t
GTP
> t
GTA
)
Figure 4 - Guard Time Adjustment
5
Zarlink Semiconductor Inc.
