®
S E M I C O N D U C T O R S
MUSIC
I
MU9C3480A
LANCAM
®
PRELIMINARY DATA SHEET DRAFT
DISTINCTIVE CHARACTERISTICS
• 256 x 64-bit CMOS Content-addressable Memory (CAM)
with 16-bit I/O for compatibility with the MU9C5480
• New faster compare speed of 70 ns.
• Dual configuration register set (Control, Segment
Control, Mask Register 1, Address Register, and
Persistent Source and Destination) for rapid context
switching
• Shiftable Comparand and Mask Register 2 to assist in
proximate matching algorithms
• Increased flexibility of the patented CAM/RAM
partitioning
• Added /MA and /MM output flags to enable faster
system performance
• Readable Device ID
• Selectable faster operating mode with no wait states
after a no-match
• Validity bits of entries are stored in the Status register
after a read or move from memory operation
• Single cycle reset for Segment Control register
• External Reset pin works in parallel to internal Power
On Reset circuitry
• Packaged in an industry-standard 44-pin PLCC
package to be socket compatible with the MU9C5480A,
MU9C1480A and MU9C2480A.
• Low power off a 5 volt supply
BLOCK DIAGRAM
LEGEND
MUX
DATA (16)
I/O BUFFERS
DATA (64)
VCC
GND
= LOGIC
DATA (16)
TRANSLATE
802.3/802.5
DATA (16)
DEMUX
DATA (64)
= REGISTERS
AND MEMORY
* = DEFAULT
W/O = WRITE ONLY
R/O = READ ONLY
DQ (15–0)
(16)
COMMANDS & STATUS
(16)
SOURCE AND
DESTINATION
SEGMENT
COUNTERS
ADDRESS DECODER
COMPARAND*
MASK 1
MASK 2
256 X 2 VALIDITY BITS
PRIORITY ENCODER
/MA
/MM
/E
/W
/CM
/RESET
INSTRUCTION (W/O)*
CONTROL
ADDRESS ADDRESS
NEXT FREE ADDRESS (R/O)
CONTROL
16
SEGMENT CONTROL
PAGE ADDRESS (LOCAL)
DEVICE SELECT (GLOBAL)
STATUS (15-0) (R/O)*
STATUS (31-16) (R/O)
REGISTER SET
MATCH ADDR
& /MA FLAG
/MM, /FL
9
2
8
CAM ARRAY
256 WORDS
X 64 BITS
2
/EC
/FF
MATCH
AND
FLAG
LOGIC
/FI
/MF
/MI
GENERAL DESCRIPTION
The MU9C3480A LANCAM is a 256 x 64-bit Content-
addressable Memory (CAM), designed for address filtering
applications in Local-area Network (LAN) bridges and routers.
The architecture of the LANCAM allows a network station list
of any length to be searched in a single memory transaction.
This device is also well-suited for other high-speed data search
applications such as virtual memories, optical and magnetic
disk caches, data base accelerators, data compressors, and
image processors.
Content-addressable Memories, also known as Associative
Memories, operate in the converse way to Random Access
Memories. In a RAM, the input to the device is an address, and
the output is the data stored at that address. In a CAM, the input
is a data sample and the output is a flag to indicate a match and
the address of the matching data. As a result, a CAM searches
large data bases for matching data in a short, constant time
period, no matter how many entries are in the data base. The
ability to search data words up to 64 bits wide allows large
address spaces to be searched rapidly and efficiently. A
patented architecture links each CAM entry to associated data
and makes this data available for use after a successful
compare operation.
LANCAM, the MUSIC logo, and the phrase “MUSIC Semiconductors” are registered trademarks of MUSIC Semiconductors.
MUSIC is a trademark of MUSIC Semiconductors. Certain features of this device are patented under US Patent 5,383,146.
15 April 1997 Rev. 1.0 Draft
Web
MU9C3480A
LANCAM
®
OPERATIONAL OVERVIEW
To use the LANCAM, the user loads the data into the
Comparand register, which is automatically compared
to all valid CAM locations. The device then indicates
whether or not one or more of the valid CAM locations
contains data that matches the target data. The status
of each CAM location is determined by two validity bits
at each memory location. The two bits are encoded to
render four validity conditions: Valid, Skip, Empty, and
Random Access. The memory can be partitioned into
CAM and associated RAM segments on 16-bit
boundaries. By using one of the two available mask
registers, the CAM/RAM partitioning can effectively be
set at any arbitrary size between zero and 64 bits.
The MU9C3480A LANCAM's internal data path is 64
bits wide for rapid internal comparison and data
movement. A data translation facility converts between
IEEE 802.3 (CSMA/CD "Ethernet") and 802.5 (Token
Ring) address formats. Vertical cascading of additional
LANCAMs in a daisy-chain fashion extends the CAM
memory depth for large data bases. Cascading
requires no external logic. Loading data to the Control,
Comparand a mask registers automatically triggers a
compare, and compares may also be initiated by a
command to the device. Associated RAM data is
available immediately after a successful compare
operation. The Status register reports the results of
compares including all flags and addresses. Two mask
registers are available and can be used in two different
ways: to mask comparisons or to mask data writes. The
random access validity flag allows additional masks to
be stored in the CAM array where they may be
retrieved rapidly.
The device is controlled by a simple four-wire control
interface and commands loaded into the Instruction
decoder. A powerful instruction set increases the
control flexibility and minimizes software overhead.
Additionally, dedicated pins for match and
multiple-match flags enhance performance when the
device is controlled by a state machine. These and
other features make the LANCAM a powerful
associative memory that drastically reduces search
delays.
Skip Bit
0
0
1
Empty Bit
0
1
0
Entry Type
Valid
Empty
Skip
1
1
RAM
Table 1: Entry Types vs. Validity Bits
/MM
/FF
/FI
/CM
/EC
GND
DQ0
DQ1
DQ2
DQ3
NC
40
41
42
43
44
1
2
3
4
5
6
39
38
37
36
35
34
33
32
31
30
29
NC
DQ4
DQ5
NC
VCC
NC
GND
GND
DQ6
DQ7
NC
7
8
9
10
11
12
13
14
15
16
17
44-pin PLCC
(Top View)
/MA
/MI
/MF
GND
/RESET
VCC
VCC
NC
/E
/W
NC
Figure 1: Pinout Diagram
PIN DESCRIPTIONS
All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash ("/") are active LOW. Inputs
(except for the RESET pin) should never be left floating. The CAM architecture draws large currents during compare operations,
mandating the use of good layout and bypassing techniques. Refer to the Electrical Characteristics section for more information.
DQ15-DQ0 (Data Bus, I/O, Three-state TTL)
The DQ15-DQ0 lines convey data, commands and status
to and from the MU9C3480A. The direction and nature of
the information that flows to or from the device is
controlled by the states of /W and /CM, respectively.
When /E is HIGH, DQ15-DQ0 go to Hi-Z.
Rev. 1.0 Draft
Web
2
28
27
26
25
24
23
22
21
20
19
18
NC
DQ15
DQ14
DQ13
DQ12
GND
DQ11
DQ10
DQ9
DQ8
NC
/E
(Chip Enable, Input, TTL)
The /E input enables the device while LOW. The falling
edge registers the control signals /W, /CM, /EC. The
rising edge locks the daisy chain, turns off the DQ pins,
and clocks the Destination and Source Segment
counters. The four cycle types enabled by /E are shown
in Table 2.
MU9C3480A
LANCAM
®
PIN DESCRIPTIONS (CONT’D)
/W
(Write Enable, Input, TTL)
/MA
(Device Match Flag, Output, TTL)
The /W input selects the direction of data flow during a
device cycle. /W LOW selects a Write cycle, and /W
HIGH selects a Read cycle.
/CM
(Data/Command Select, Input, TTL)
The /MA output is LOW when one or more valid
matches occur during the current or the last previous
compare cycle. The /MA output is not qualified by /EC
or /MI, and reflects the match flag from that specific
device’s Status register. /MA will be reset when the
active register set is changed.
/MM
(Device Multiple Match Flag, Output, TTL)
The /CM input selects whether the input signals on
DQ15-DQ0 are data or commands. /CM LOW selects
Command cycles, and /CM HIGH selects Data cycles.
/EC
(Enable Daisy Chain, Input, TTL)
The /EC signal performs two functions. The /EC input
enables the /MF output to show the results of a
comparison. If /EC is LOW at the falling edge of /E in
a given cycle, the /MF output is enabled. Otherwise, the
/MF output is held HIGH. The /EC signal also enables
the /MF-/MI daisy-chain, which serves to select the
device with the highest-priority match in a string of
LANCAMs. Tables 8a and 8b explain the effect of the
/EC signal on a device with and without a match in both
the 1480 and 2480 modes. /EC must be HIGH during
initialization.
/MF
(Match Flag, Output, TTL)
The /MM output is LOW when more than one valid
match occurs during the current or the last previous
compare cycle. The /MM output is not qualified by /EC
or /MI, and reflects the multiple match flag from that
specific device’s Status register. /MM will be reset when
the active register set is changed.
/FF
(Full Flag, Output, TTL)
The /MF output goes LOW when one or more valid
matches occur during a compare cycle. /MF becomes
valid after /E goes HIGH on the cycle that enables the
daisy chain (the first cycle that /EC is registered LOW
by the previous falling edge of /E; see Figure 6). In a
daisy-chain, valid match(es) in higher priority devices
are passed from the /MI input to /MF. If the daisy chain
is enabled but the match flag is disabled in the control
register, the /MF output only depends on the /MI input
of the device (/MF=/MI). /MF is HIGH if there is no
match or when the daisy chain is disabled (/E goes
HIGH when /EC was HIGH on the previous falling edge
of /E). The System Match flag is the /MF pin of the last
device in the daisy-chain. /MF will be reset when the
active configuration register set is changed.
/MI
(Match Input, Input, TTL)
If enabled in the control register, the /FF output goes
LOW when no empty memory locations exist within the
device (and in the daisy-chain above the device as
indicated by the /FI pin). The System Full flag is the /FF
pin of the last device in the daisy chain, and the Next
Free address resides in the device with /FI LOW and
/FF HIGH. If disabled in the control register, the /FF
output only depends on the /FI input (/FF = /FI).
/FI
(Full Input, Input, TTL)
The /FI input generates a CAM-Memory-System-Full
indication in vertically cascaded systems. It is
connected to the /FF output of the previous (next-higher
priority) device in the daisy chain. The /FI pin on the
highest priority device must be tied LOW.
/RESET (Reset, Input, TTL)
Driving the /RESET pin LOW resets the device to the
conditions shown in Table 5. The hardware reset
operates in parallel with the internal Power-on-reset
circuitry, which sets the device to the same conditions.
For compatibility with the MU9C5480, the /RESET pin
has an internal pull-up resistor and may be left
unconnected. The /RESET pin should be driven by TTL
levels, not directly by an RC timeout. /E must be kept
HIGH during /RESET.
VCC, GND
(Positive Power Supply, Ground)
The /MI input prioritizes devices in vertically cascaded
systems. It is connected to the /MF output of the
previous (next higher-priority) device in the daisy chain.
The /MI pin on the highest priority device must be tied
HIGH.
/W
LOW
LOW
HIGH
HIGH
/CM
LOW
HIGH
LOW
HIGH
Cycle Type
Command Write Cycle
Data Write Cycle
Command Read Cycle
Data Read Cycle
These pins are the power supply connections to the
MU9C3480A. VCC must meet the requirements in the
Operating Conditions section relative to the GND pins,
which are at 0 Volts (system reference potential), for
correct operation of the device. The ground
connections on pins 1 and 23 are connected to the
internal ground system and may be left unconnected for
compatibility with existing MU9C5480 layouts;
however, they must be connected to the ground plane
for 70ns performance.
Table 2: I/O Cycles
Rev. 1.0 DraftWeb
3
MU9C3480A
LANCAM
®
FUNCTIONAL DESCRIPTION
The MU9C3480A LANCAM is a 256 x 64-bit
Content-addressable Memory (CAM) for network
address filtering, virtual memory, data compression,
cache, and table look-up applications. The MU9C3480A
contains 16,384 (16K) usable bits of static CAM,
organized as 256 64-bit Data fields. Each Data field can
be partitioned into a CAM and a RAM subfield on 16-bit
boundaries. The contents of the memory can be
randomly accessed or associatively accessed by the
use of a compare. During automatic Comparison cycles,
data in the Comparand register is automatically
compared with the “Valid” CAM section of the memory
array. The device ID of 341H can be read using a TCO
PS instruction.
The data inputs and outputs of the MU9C3480A
LANCAM are multiplexed for data and instructions over
a 16-bit I/O bus. Internally, data is handled on a 64-bit
basis, since the Comparand register, the Mask
registers, and each memory entry is 64 bits wide.
Memory entries are globally configurable into CAM and
RAM segments on 16-bit boundaries, as described in
US
Patent
5,383,146
assigned
to
MUSIC
Semiconductors. Seven different CAM/RAM splits are
possible, with the CAM width going from one to four
segments, and the remaining RAM width going from
three to zero segments. Finer resolution on compare
width is possible by invoking a Mask register during a
compare, which does global masking on a bit basis. The
CAM subfield contains the Associative data which
enters into Compares, while the RAM subfield contains
the Associated data which is not compared. In LAN
Bridges, the RAM subfield could hold, for example,
port-address and aging information related to the
destination or source address information held in the
CAM subfield of a given location. In a translation
application, the CAM field could hold the dictionary
entries, while the RAM field holds the translations, with
almost instantaneous response.
Each entry has two validity bits (known as Skip bit and
Empty bit) associated with it to define its particular type:
Empty, Valid, Skip, or RAM. When data is written to the
active Comparand register and the active Segment
Control register reaches its terminal count, the contents
of the Comparand register are automatically compared
with the CAM portion of all the Valid entries in the
memory array. For added versatility, the Comparand
register can be barrel-shifted right or left one bit at a
time. A Compare instruction can then be used to force
another compare between the Comparand register and
the CAM portion of memory entries of any one of the four
validity types. After a Read or Move from Memory
operation, the validity bits of the location read or moved
will be copied into the Status register, where they can be
read from the Status register using Command Read
cycles.
Data can be moved from one of the data registers (CR,
MR1, or MR2) to a memory location that is based on the
Rev. 1.0 Draft
Web
4
results of the last comparison (Highest Priority Match or
Next free), or to an absolute address, or to the location
pointed to by the active Address register. Data can also
be written directly to the memory from the DQ bus using
any of the above addressing modes, with the Address
register directly loaded or set to increment or
decrement, allowing DMA-type reading or writing from
memory.
Two sets of configuration registers (Control, Segment
Control, Address, Mask Register 1, and the Persistent
Source and Destination) are provided to permit rapid
context switching between foreground and background
activities. Writes, reads, moves and compares are
controlled by the currently active set of configuration
registers. The foreground set would typically be
pre-loaded with values useful for comparing input data,
often called filtering, while the background set would be
pre-loaded with values useful for housekeeping
activities such as purging old entries. Moving from the
foreground task of filtering to the background task of
purging can be done by issuing a single instruction to
change the current set of configuration registers. The
match condition of the device is reset whenever the
active register set is changed.
The active Control register determines the operating
conditions within the device. Conditions set by this
register's contents are Reset, enable or disable Match
flag, enable or disable Full flag, default data translation,
CAM/RAM partitioning, disable or select masking
conditions, disable or select auto-incrementing or
-decrementing the Address register, and to set
1480-compatible or 2480-enhanced modes. The active
Segment Control register contains separate counters to
control the writing of 16-bit data segments to the
selected persistent destination, and to control the
reading of 16-bit data segments from the selected
persistent source.
There are two active Mask registers at any one time,
which can be selected to mask comparisons or data
writes. Mask Register 1 has both a foreground and
background mode to support rapid context switching.
Mask Register 2 does not have this mode, but can be
shifted left or right one bit at a time. For masking
comparisons, data stored in the active selected Mask
register determines which bits of the Comparand are
compared against the valid contents of the Memory. If
a bit is set HIGH in the Mask register, the same bit
position in the Comparand register becomes a “don't
care” for the purpose of the comparison with all the
memory locations. During a Write cycle, data in the
selected active Mask register can also determine which
bits in the destination will be updated. If a bit is HIGH in
the Mask register, the corresponding bit of the
destination is unchanged during the Write cycle.
The Match line associated with each memory address
is fed into a Priority encoder where multiple responses
MU9C3480A
LANCAM
®
FUNCTIONAL DESCRIPTION (CONT’D)
are resolved, and the address of the highest-priority
responder (the lowest numerical match address) is
generated. In the LAN Bridge application, a multiple
response might indicate an error. In other applications
the existence of multiple responders may be valid.
Control of these devices is via four input control signals
and by commands loaded into an Instruction decoder.
Two of the four input control signals determine the cycle
type. The control signals tell the device whether the
data on the I/O bus represents Data or a Command,
and is Input or Output. Commands are decoded by
Instruction logic and control moves, forced compares,
validity bit manipulations, and the data path within the
device. Registers (Control, Segment Control, Address,
Next Free Address, etc.) are accessed using
Temporary Command Override instructions. The data
path from the DQ bus to/from data resources
(Comparand, Masks, and Memory) within the device
are set until changed by Select Persistent Source and
Destination instructions.
After a Compare cycle caused by either a Data Write to
the Comparand or Mask registers or a forced Compare,
the Status register contains the address of the Highest
Priority Matching location in that device, concatenated
with its Page Address, along with flags indicating
internal Match, Multiple Match, and Full. When the
Status register is read with a Command Read cycle, the
device with the Highest Priority match will respond,
outputting the System Match Address to the DQ bus.
The internal Match (/MA) and Multiple match (/MM)
flags are also output on pins. Another set of flags (/MF
and /FF) that are qualified by the match and full flags
of previous devices in the system are also available
directly on output pins, and are independently
daisy-chained to provide System Match and Full flags
in vertically cascaded LANCAM arrays. In such arrays,
PA=0000h
DQ15–0
/E
/W
/CM
/EC
16
DQ15–0
/MI
/E
/FI
/W
LANCAM
/FF
/CM
/EC
/MF
Vcc
if no match occurs during a comparison, read access to
the memory, and all the registers except the Next Free
Register, is denied to prevent device contention. In a
daisy chain, all devices will respond to Command and
Data Writes, depending on the conditions shown in
Tables 8a and 8b, unless the operation involves the
Highest Priority Match address or the Next Free
Address; in which case, only the specific device having
the Highest Priority Match or the Next Free Address will
respond.
A Page Address register in each device simplifies
vertical expansion in systems using more than one
LANCAM. This register is loaded with a specific device
address during system initialization, which then serves
as the higher-order address bits. A Device Select
register allows the user to target a specific device within
a vertically cascaded system by setting it equal to the
Page Address register value, or to address all the
devices in a string at the same time by setting the
Device Select value to FFFFH.
Figure 2a shows expansion using a daisy-chain. Note
that system flags are generated without the need for
external logic. The Page Address register allows each
device in the vertically cascaded chain to supply its own
address in the event of a match eliminating the need for
an external Priority encoder to calculate the complete
Match address at the expense of the ripple-through time
to resolve the Highest-priority match. The Full flag
daisy-chaining allows Associative writes using a Move
to Next Free Address instruction which does not need
a supplied address.
Figure 2b shows an external PLD implementation of a
simple priority encoder to resolve the Highest-priority
match and gate the /E signal to each device for systems
requiring maximum performance.
/E
/GLOBAL
/E
LANCAM
/MA
PA=0001h
DQ15–0
/MI
/E
/FI
/W
LANCAM
/FF
/CM
/EC
/MF
/E
LANCAM
/MA
PLD
/E
LANCAM
/MA
/E
PA=0007h
DQ15–0
/MI
/E
/FI
/W
LANCAM
/FF
/CM
/EC
/MF
LANCAM
/MA
SYSTEM FULL
SYSTEM MATCH
Figure 2a: Vertical Cascading
5
Figure 2b: External Prioritizing
Rev. 1.0 DraftWeb
