Preliminary Data Sheet
MU9C4480A/L LANCAMs
®
APPLICATION BENEFITS
The 4096 x 64 bit LANCAM facilitates numerous
operations:
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New speed grade allows processing of both
DA and SA within 560 ns, equivalent to 111,
10 Base-T or 11, 100 Base-T Ethernet ports
Higher density enables longer station lists
DISTINCTIVE CHARACTERISTICS
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4096 x 64-bit CMOS content-addressable memory
(CAM)
16-bit I/O
Fast 70 ns compare speed
Dual configuration register set for rapid context
switching
16-bit CAM/RAM segments with MUSIC’s patented
partitioning
/MA and /MM output flags to enable faster system
performance
Readable Device ID
Selectable faster operating mode with no wait states
after a no-match
44-pin PLCC package
5 volt (4480A) or 3.3 volt (4480L) operation
Industrial temperature grade available
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Expanded powerful instruction set for any list
processing needs
Fully Compatible with all MUSIC LANCAM
Series, cascadable to any practical length
without performance penalties
Full CAM features allow all operations mask,
on a bit per bit basis
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M UX
D A TA (1 6 )
D A TA (6 4 )
V CC
I/O B U FFE R S
G ND
TR A N S L A TE
8 0 2.3 /8 02 .5
D Q (1 5 – 0)
(1 6 )
D A TA (1 6 )
D A TA (1 6 )
DE M UX
D A TA (6 4 )
C O M M A N D S & S TA TU S
(1 6 )
S O URCE AND
D E S TIN A TIO N
S E G M E NT
C O U N TE R S
CO M P ARAND*
M AS K 1
M AS K 2
/MA
/M M
ADDRE S S DE CO DE R
4 K X 2 V A L IDITY B ITS
IN S TR U C TIO N ( W /O )*
/W
C O N TR O L
N E X T FR E E A D D R E S S (R /O )
/C M
C O N TR O L
/R E S E T
16
P A G E A D D R E S S (LO C A L)
D E V IC E S E LE C T (G LO B A L)
/E C
S TA TU S (1 5 -0 ) ( R /O )*
/M M , /FL
S TA TU S (3 1 -1 6 ) (R /O )
R E G IS TE R S E T
2
M A TC H A D D R
& / M A FL A G
13
S E G M E N T C O N TR O L
ADDRE S S ADDRE S S
12
C A M A R R AY
40 9 6 W OR D S
X 6 4 B I TS
P R IO R ITY E N C O D E R
/E
2
/FF
M A TC H
AND
FLA G
LO G IC
/FI
/M F
/MI
Block Diagram
LANCAM, the MUSIC logo, and the phrase “MUSIC Semiconductors” are registered trademarks of MUSIC Semiconductors. MUSIC is
a trademark of MUSIC Semiconductors. Certain features of this device are patented under US Patent 5,383,146.
1 October 1998 Rev. 3a
MU9C4480A/L
GENERAL DESCRIPTION
The MU9C4480A and MU9C4480L LANCAMs are 4096
x 64-bit content-addressable memories (CAMs), with 16-bit
wide interfaces. They are pin compatible with all devices in
the MUSIC LANCAM family.
Content-addressable memories, also known as associative
memories, operate in the converse way to random access
memories (RAM). In RAM, the input to the device is an
address and the output is the data stored at that address.
In CAM, the input is a data sample and the output is a flag
to indicate a match and the address of the matching data.
As a result, CAM searches large databases for matching
data in a short, constant time period, no matter how many
entries are in the database. The ability to search data words
up to 64 bits wide allows large address spaces to be searched
rapidly and efficiently. A patented architecture links each
CAM entry to associated data and makes this data available
for use after a successful compare operation.
The MUSIC LANCAMs are ideal for address filtering and
translation applications in LAN switches and routers. The
LANCAMs are also well suited to encryption, database
accelerators, and image processing.
OPERATIONAL OVERVIEW
To use the LANCAM, the user loads the data into the
Comparand register, which is automatically compared to all
valid CAM locations. The device then indicates whether or
not one or more of the valid CAM locations contains data
that matches the target data. The status of each CAM
location is determined by two validity bits at each memory
location. The two bits are encoded to render four validity
conditions: Valid, Skip, Empty, and Random Access, as
shown in Table 1. The memory can be partitioned into CAM
and associated RAM segments on 16-bit boundaries, but
by using either of the two available mask registers, the
CAM/RAM partitioning can be set at any arbitrary size
between zero and 64 bits.
The LANCAM’s internal data path is 64 bits wide for rapid
internal comparison and data movement. Vertical cascading
of additional LANCAMs in a daisy chain fashion extends
the CAM memory depth for large databases. Cascading
requires no external logic. Loading data to the Control,
Comparand, and mask registers automatically triggers a
compare. Compares may also be initiated by a command to
Skip Bit
0
0
1
1
Empty Bit
0
1
0
1
Entry Type
Valid
Empty
Skip
RAM
the device. Associated RAM data is available immediately
after a successful compare operation. The Status register
reports the results of compares including all flags and
addresses. Two mask registers are available and can be used
in two different ways: to mask comparisons or to mask data
writes. The random access validity type allows additional
masks to be stored in the CAM array where they may be
retrieved rapidly.
The device is controlled by a simple four-wire control interface
and commands loaded into the Instruction Decoder. A
powerful instruction set increases the control flexibility and
minimizes software overhead. Additionally, dedicated pins for
match and multiple-match flags enhance performance when
the device is controlled by a state machine. These and other
features make the LANCAM a powerful associative memory
that drastically reduces search delays.
G ND
D Q0
D Q1
D Q2
D Q3
V CC
/ MM
/ FF
/ FI
/C M
/EC
43
44
1
2
3
4
5
6
40
41
42
Table 1: Entry Types vs. Validity Bits
/W
LOW
LOW
HIGH
HIGH
/CM
Cycle Type
LOW
Command Write Cycle
HIGH
Data Write Cycle
LOW
Command Read Cycle
HIGH
Data Read Cycle
Table 2: I/O Cycles
2
G ND
DQ4
DQ5
V CC
V CC
TE S T 2
G ND
G ND
DQ6
DQ7
V CC
7
8
9
10
11
12
13
14
15
16
17
18
G ND
44-pin PLCC
4 4 -pi n P L CC
(Top View)
(Top V ie w )
39
38
37
36
35
34
33
32
31
30
29
/M A
/ MI
/ MF
G ND
/R ESET
V CC
V CC
TE S T1
/E
/W
G ND
PINOUT DIAGRAM
24
23
22
21
20
19
D Q9
D Q8
28
27
26
25
G ND
D Q15
D Q14
D Q13
D Q12
G ND
D Q11
D Q10
Rev. 3a
MU9C4480A/L
PIN DESCRIPTIONS
All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active LOW. Inputs should
never be left floating. The CAM architecture draws large currents during compare operations, mandating the use of good layout and
bypassing techniques. Refer to the Electrical Characteristics section for more information.
/E (Chip Enable, Input, TTL)
The /E input enables the device while LOW. The falling edge
registers the control signals /W, /CM, and /EC. The rising
edge locks the daisy chain, turns off the DQ pins, and clocks
the Destination and Source Segment counters. The four cycle
types enabled by /E are shown in Table 2.
/W (Write Enable, Input, TTL)
The /W input selects the direction of data flow during a device
cycle. /W LOW selects a Write cycle and /W HIGH selects a
Read cycle.
/CM (Data/Command Select, Input, TTL)
The /CM input selects whether the input signals on
DQ15–0 are data or commands. /CM LOW selects Command
cycles and /CM HIGH selects Data cycles.
/EC (Enable Daisy Chain, Input, TTL)
The /EC signal performs two functions. The /EC input enables
the /MF output to show the results of a comparison, as shown
in Figure 6 on page 14. If /EC is LOW at the falling edge of /E
in a given cycle, the /MF output is enabled. Otherwise, the
/MF output is held HIGH. The /EC signal also enables the
/MF–/MI daisy chain, which serves to select the device with
the highest-priority match in a string of LANCAMs. Tables 5a
and 5b on page 11 explain the effect of the /EC signal on a
device with or without a match in both Standard and Enhanced
modes. /EC must be HIGH during initialization.
DQ15–0 (Data Bus, I/O, TTL)
The DQ15–0 lines convey data, commands, and status to and
from the LANCAM. The direction and nature of the information
that flows to or from the device are controlled by /W and /CM.
When /E is HIGH, DQ15–0 go to Hi-Z.
/MF (Match Flag, Output, TTL)
The /MF output goes LOW when one or more valid matches
occur during a compare cycle. /MF becomes valid after /E
goes HIGH on the cycle that enables the daisy chain (on the
first cycle that /EC is registered LOW by the previous falling
edge of /E; see Figure 6 on page 14). In a daisy chain, valid
match(es) in higher priority devices are passed from the /MI
input to /MF. If the daisy chain is enabled but the match flag is
disabled in the Control register, the /MF output only depends
on the /MI input of the device (/MF=/MI). /MF is HIGH if
there is no match or when the daisy chain is disabled (/E goes
HIGH when /EC was HIGH on the previous falling edge of /E).
The System Match flag is the /MF pin of the last device in the
3
daisy chain. /MF will be reset when the active configuration
register set is changed.
/MI (Match Input, Input, TTL)
The /MI input prioritizes devices in vertically cascaded
systems. It is connected to the /MF output of the previous
device in the daisy chain. The /MI pin on the first device in the
chain must be tied HIGH.
/MA (Device Match Flag, Output, TTL)
The /MA output is LOW when one or more valid matches
occur during the current or the last previous compare cycle.
The /MA output is not qualified by /EC or /MI, and reflects
the match flag from that specific device’s Status register. /MA
will be reset when the active register set is changed.
/MM (Device Multiple Match Flag, Output, TTL)
The /MM output is LOW when more than one valid match
occurs during the current or the last previous compare cycle.
The /MM output is not qualified by /EC or /MI, and reflects
the multiple match flag from that specific device’s Status
register. /MM will be reset when the active register set is changed.
/FF (Full Flag, Output, TTL)
If enabled in the Control register, the /FF output goes LOW
when no empty memory locations exist within the device (and
in the daisy chain above the device as indicated by the /FI
pin). The System Full flag is the /FF pin of the last device in the
daisy chain, and the Next Free address resides in the device
with /FI LOW and /FF HIGH. If disabled in the Control register,
the /FF output only depends on the /FI input (/FF = /FI).
/FI (Full Input, Input, TTL)
The /FI input generates a CAM-Memory-System-Full
indication in vertically cascaded systems. It is connected to
the /FF output of the previous device in the daisy chain. The
/FI pin on the first device in a chain must be tied LOW.
/RESET (Reset, Input, TTL)
/RESET must be driven LOW to place the device in a known
state before operation, which will reset the device to the
conditions shown in Table 4 on page 9. LANCAM ‘A’ devices
have a hardware reset that operates in parallel with the internal
Power-on-reset circuitry, and sets the device to the same
condition. For compatibility with the MU9C1480, the /RESET
pin has an internal pull-up resistor and may be left unconnected.
The /RESET pin should be driven by TTL levels, not directly by
an RC timeout. /E must be kept HIGH during /RESET.
Rev. 3a
MU9C4480A/L
PIN DESCRIPTIONS
Continued
TEST1, TEST2 (Test, Input, TTL)
These pins enable MUSIC production test modes that are
not usable in an application. They should be connected to
ground, either directly or through a pull-down resistor, or
they may be left unconnected. These pins may not be
implemented on all versions of these products.
VCC, GND (Positive Power Supply, Ground)
These pins are the power supply connections to the
LANCAM. VCC must meet the voltage supply requirements
in the Operating Conditions section relative to the GND
pins, which are at 0 Volts (system reference potential), for
correct operation of the device. All the ground and power
pins must be connected to their respective planes with
adequate bulk and high frequency bypassing capacitors in
close proximity to the device.
FUNCTIONAL DESCRIPTION
The LANCAM is a content-addressable memory (CAM)
with 16-bit I/O for network address filtering and translation,
virtual memory, data compression, caching, and table lookup
applications. The memory consists of static CAM,
organized in 64-bit data fields. Each data field can be
partitioned into a CAM and a RAM subfield on 16-bit
boundaries. The contents of the memory can be randomly
accessed or associatively accessed by the use of a compare.
During automatic comparison cycles, data in the
Comparand register is automatically compared with the
“Valid” entries in the memory array. The Device ID can be
read using a TCO PS instruction (see Table 12 on page 21).
The data inputs and outputs of the LANCAM are
multiplexed for data and instructions over a 16-bit
I/O bus. Internally, data is handled on a 64-bit basis, since
the Comparand register, the mask registers, and each
memory entry are 64 bits wide. Memory entries are globally
configurable into CAM and RAM segments on 16-bit
boundaries, as described in US Patent 5,383,146 assigned
to MUSIC Semiconductors. Seven different CAM/RAM
splits are possible, with the CAM width going from one to
four segments, and the remaining RAM width going from
three to zero segments. Finer resolution on compare width
is possible by invoking a mask register during a compare,
which does global masking on a bit basis. The CAM subfield
contains the associative data, which enters into compares,
while the RAM subfield contains the associated data, which
is not compared. In LAN bridges, the RAM subfield could
hold, for example, port-address and aging information
related to the destination or source address information
held in the CAM subfield of a given location. In a translation
application, the CAM field could hold the dictionary entries,
while the RAM field holds the translations, with almost
instantaneous response.
Each entry has two validity bits (known as Skip bit and Empty
bit) associated with it to define its particular type: empty, valid,
skip, or RAM. When data is written to the active Comparand
Rev. 3a
4
register, and the active Segment Control register reaches its
terminal count, the contents of the Comparand register are
automatically compared with the CAM portion of all the valid
entries in the memory array. For added versatility, the
Comparand register can be barrel-shifted right or left one bit at
a time. A Compare instruction can then be used to force
another compare between the Comparand register and the
CAM portion of memory entries of any one of the four validity
types. After a Read or Move from Memory operation, the
validity bits of the location read or moved will be copied into
the Status register, where they can be read from the Status
register using Command Read cycles.
Data can be moved from one of the data registers (CR, MR1, or
MR2) to a memory location that is based on the results of the
last comparison (Highest-Priority Match or Next Free), or to
an absolute address, or to the location pointed to by the active
Address register. Data can also be written directly to the
memory from the DQ bus using any of the above addressing
modes. The Address register may be directly loaded and may
be set to increment or decrement, allowing DMA-type reading
or writing from memory.
Two sets of configuration registers (Control, Segment
Control, Address, Mask Register 1, and Persistent Source
and Destination) are provided to permit rapid context
switching between foreground and background activities.
Writes, reads, moves, and compares are controlled by the
currently active set of configuration registers. The
foreground set would typically be pre-loaded with values
useful for comparing input data, often called filtering, while
the background set would be pre-loaded with values useful
for housekeeping activities such as purging old entries.
Moving from the foreground task of filtering to the
background task of purging can be done by issuing a single
instruction to change the current set of configuration
registers. The match condition of the device is reset
whenever the active register set is changed.
MU9C4480A/L
FUNCTIONAL DESCRIPTION
Continued
The active Control register determines the operating
conditions within the device. Conditions set by this
register’s contents are reset, enable or disable Match flag,
enable or disable Full flag, CAM/RAM partitioning, disable
or select masking conditions, disable or select auto-
incrementing or -decrementing the Address register, and
select Standard or Enhanced modes. The active Segment
Control register contains separate counters to control the
writing of 16-bit data segments to the selected persistent
destination, and to control the reading of 16-bit data
segments from the selected persistent source.
There are two active mask registers at any one time, which can
be selected to mask comparisons or data writes. Mask Register
1 has both a foreground and background mode to support
rapid context switching. Mask Register 2 does not have this
mode, but can be shifted left or right one bit at a time. For
masking comparisons, data stored in the active selected mask
register determines which bits of the comparand are compared
against the valid contents of the memory. If a bit is set HIGH in
the mask register, the same bit position in the Comparand
register becomes a “don’t care” for the purpose of the
comparison with all the memory locations. During a Data Write
cycle or a MOV instruction, data in the specified active mask
register can also determine which bits in the destination will
be updated. If a bit is HIGH in the mask register, the
corresponding bit of the destination is unchanged.
The match line associated with each memory address is fed
into a priority encoder where multiple responses are resolved,
and the address of the highest-priority responder (the lowest
numerical match address) is generated. In LAN applications, a
multiple response might indicate an error. In other applications
the existence of multiple responders may be valid.
Four input control signals and commands loaded into an
instruction decoder control the LANCAM. Two of the four
input control signals determine the cycle type. The control
signals tell the device whether the data on the I/O bus
represents data or a command, and is input or output.
Commands are decoded by instruction logic and control
moves, forced compares, validity bit manipulations, and the
data path within the device. Registers (Control, Segment
Control, Address, Next Free Address, etc.) are accessed using
Temporary Command Override instructions. The data path
from the DQ bus to/from data resources (comparand, masks,
and memory) within the device are set until changed by Select
Persistent Source and Destination instructions.
After a Compare cycle (caused by either a data write to the
Comparand or mask registers, a write to the Control register, or
a forced compare), the Status register contains the address of
the Highest-Priority Matching location in that device,
concatenated with its page address, along with flags indicating
internal match, multiple match, and full. When the Status register
is read with a Command Read cycle, the device with the
Highest-Priority match will respond, outputting the System
Match address to the DQ bus. The internal Match (/MA) and
Multiple match (/MM) flags are also output on pins. Another
set of flags (/MF and /FF) that are qualified by the match and
full flags of previous devices in the system are also available
directly on output pins, and are independently daisy-chained
to provide System Match and Full flags in vertically cascaded
LANCAM arrays. In such arrays, if no match occurs during a
comparison, read access to the memory and all the registers
except the Next Free register is denied to prevent device
contention. In a daisy chain, all devices will respond to
Command and Data Write cycles, depending on the conditions
shown in Tables 5a and 5b on page 11, unless the operation
involves the Highest-Priority Match address or the Next Free
address; in which case, only the specific device having the
Highest-Priority match or the Next Free address will respond.
A Page Address register in each device simplifies vertical
expansion in systems using more than one LANCAM. This
register is loaded with a specific device address during system
initialization, which then serves as the higher-order address
bits. A Device Select register allows the user to target a specific
device within a vertically cascaded system by setting it equal
to the Page Address Register value, or to address all the
devices in a string at the same time by setting the Device
Select value to FFFFH.
Figure 1a shows expansion using a daisy chain. Note that
system flags are generated without the need for external logic.
The Page Address register allows each device in the vertically
cascaded chain to supply its own address in the event of a
match, eliminating the need for an external priority encoder to
calculate the complete Match address at the expense of the
ripple-through time to resolve the highest-priority match. The
Full flag daisy-chaining allows Associative writes using a
Move to Next Free Address instruction which does not need
a supplied address.
Figure 1b shows an external PLD implementation of a simple
priority encoder that eliminates the daisy chain ripple-
through delays for systems requiring maximum performance
from many CAMS.
5
Rev. 3a
