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MX25V512EOI13G

512K-BIT [x 1/x 2] CMOS SERIAL FLASH

厂商名称：Macronix

厂商官网：http://www.macronix.com/en-us/Pages/default.aspx

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MX25V512E
MX25V512E
DATASHEET
P/N: PM1734
1
REV. 1.3, NOV. 13, 2013
MX25V512E
Contents
FEATURES .................................................................................................................................................................. 4
GENERAL .......................................................................................................................................................... 4
PERFORMANCE ............................................................................................................................................... 4
SOFTWARE FEATURES ................................................................................................................................... 4
HARDWARE FEATURES................................................................................................................................... 5
GENERAL DESCRIPTION ......................................................................................................................................... 5
PIN CONFIGURATIONS .............................................................................................................................................. 6
8-LAND USON (2x3mm) ................................................................................................................................... 6
8-PIN TSSOP (173mil) ...................................................................................................................................... 6
8-PIN SOP (150mil) ........................................................................................................................................... 6
PIN DESCRIPTION ...................................................................................................................................................... 6
BLOCK DIAGRAM....................................................................................................................................................... 7
DATA PROTECTION.................................................................................................................................................... 8
Table 1. Protected Area Sizes ............................................................................................................................ 9
HOLD FEATURE.......................................................................................................................................................... 9
Figure 1. Hold Condition Operation ................................................................................................................... 9
Table 2. COMMAND DEFINITION ................................................................................................................... 10
Table 3. Memory Organization ........................................................................................................................ 11
DEVICE OPERATION ................................................................................................................................................ 11
Figure 2. Serial Modes Supported.................................................................................................................... 11
COMMAND DESCRIPTION ....................................................................................................................................... 12
(1) Write Enable (WREN) ................................................................................................................................. 12
(2) Write Disable (WRDI).................................................................................................................................. 12
(3) Read Identification (RDID)
.......................................................................................................................... 12
(4) Read Status Register (RDSR) .................................................................................................................... 13
Status Register ................................................................................................................................................. 13
(5) Write Status Register (WRSR).................................................................................................................... 14
Table 4. Protection Modes ................................................................................................................................ 14
(6) Read Data Bytes (READ) ........................................................................................................................... 15
(7) Read Data Bytes at Higher Speed (FAST_READ) ..................................................................................... 15
(8) Dual Output Mode (DREAD) ....................................................................................................................... 15
(9) Sector Erase (SE) ....................................................................................................................................... 15
(10) Block Erase (BE)....................................................................................................................................... 16
(11) Chip Erase (CE) ........................................................................................................................................ 16
(12) Page Program (PP)................................................................................................................................... 16
(13) Deep Power-down (DP) ............................................................................................................................ 17
(14) Release from Deep Power-down (RDP), Read Electronic Signature (RES) ........................................... 17
(15) Read Electronic Manufacturer ID & Device ID (REMS) ............................................................................ 18
Table of ID Definitions
...................................................................................................................................... 18
POWER-ON STATE ................................................................................................................................................... 19
P/N: PM1734
2
REV. 1.3, NOV. 13, 2013
MX25V512E
ELECTRICAL SPECIFICATIONS .............................................................................................................................. 20
ABSOLUTE MAXIMUM RATINGS ................................................................................................................... 20
Figure 3.Maximum Negative Overshoot Waveform ......................................................................................... 20
CAPACITANCE TA = 25°C, f = 1.0 MHz........................................................................................................... 20
Figure 4. Maximum Positive Overshoot Waveform .......................................................................................... 20
Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL............................................................ 21
Figure 6. OUTPUT LOADING ......................................................................................................................... 21
Table 5. DC CHARACTERISTICS ................................................................................................................... 22
Table 6. AC CHARACTERISTICS .................................................................................................................. 23
Table 7. Power-Up Timing ................................................................................................................................ 24
INITIAL DELIVERY STATE............................................................................................................................... 24
Figure 7. Serial Input Timing ............................................................................................................................ 24
Figure 8. Output Timing .................................................................................................................................... 24
Figure 9. Hold Timing ....................................................................................................................................... 25
Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1 ............................................. 25
Figure 11. Write Enable (WREN) Sequence (Command 06) ........................................................................... 26
Figure 12. Write Disable (WRDI) Sequence (Command 04)............................................................................ 26
Figure 13. Read Identification (RDID) Sequence (Command 9F)
.................................................................... 26
Figure 14. Read Status Register (RDSR) Sequence (Command 05) .............................................................. 27
Figure 15. Write Status Register (WRSR) Sequence (Command 01).............................................................. 27
Figure 16. Read Data Bytes (READ) Sequence (Command 03) .................................................................... 27
Figure 17. Read at Higher Speed (FAST_READ) Sequence (Command 0B) ................................................. 28
Figure 18. Dual Output Read Mode Sequence (Command 3B) ....................................................................... 28
Figure 19. Page Program (PP) Sequence (Command 02)............................................................................... 29
Figure 20. Sector Erase (SE) Sequence (Command 20) ................................................................................. 30
Figure 21. Block Erase (BE) Sequence (Command 52 or D8) ......................................................................... 30
Figure 22. Chip Erase (CE) Sequence (Command 60 or C7) ......................................................................... 31
Figure 23. Deep Power-down (DP) Sequence (Command B9)....................................................................... 31
Figure 24. Read Electronic Signature (RES) Sequence (Command AB) ......................................................... 31
Figure 25. Release from Deep Power-down (RDP) Sequence (Command AB) .............................................. 32
Figure 26. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90)............................. 32
Figure 27. Power-up Timing ............................................................................................................................. 33
RECOMMENDED OPERATING CONDITIONS ......................................................................................................... 34
Figure 28. AC Timing at Device Power-Up ....................................................................................................... 34
Figure 29. Power-Down Sequence .................................................................................................................. 35
ERASE AND PROGRAMMING PERFORMANCE .................................................................................................... 36
DATA RETENTION .................................................................................................................................................... 36
LATCH-UP CHARACTERISTICS .............................................................................................................................. 36
ORDERING INFORMATION ...................................................................................................................................... 37
PART NAME DESCRIPTION ..................................................................................................................................... 38
PACKAGE INFORMATION ........................................................................................................................................ 39
REVISION HISTORY ................................................................................................................................................. 42
P/N: PM1734
3
REV. 1.3, NOV. 13, 2013
MX25V512E
512K-BIT [x 1/x 2] CMOS SERIAL FLASH
FEATURES
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 524,288 x 1 bit structure or 262,144 x 2 bits (Dual Output mode) Structure
• 16 Equal Sectors with 4K byte each
- Any Sector can be erased individually
• Single Power Supply Operation
- 2.35 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
- Fast access time: 75MHz serial clock
- Serial clock of Dual Output mode: 70MHz
- Fast program time: 0.6ms(typ.) and 1ms(max.)/page (256-byte per page)
- Byte program time: 9us
- Fast erase time: 40ms(typ.)/sector (4K-byte per sector) ; 0.5s(typ.) and 1s(max.)/chip
• Low Power Consumption
- Low active read current: 12mA(max.) at 75MHz and 4mA(max.) at 33MHz
- Low active programming current: 15mA (typ.)
- Low active sector erase current: 9mA (typ.)
- Low standby current: 15uA (typ.)
- Deep power-down mode 2uA (typ.)
• Minimum 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Block Lock protection
- The BP0~BP1 status bit defines the size of the area to be software protected against Program and Erase in-
structions.
• Auto Erase and Auto Program Algorithm
program pulse widths (Any page to be programed should have page in the erased state first)
•
Status Register Feature
•
Electronic Identification
-
Automatically erases and verifies data at selected sector
-
Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
-
JEDEC 2-byte Device ID
- RES command, 1-byte Device ID
P/N: PM1734
4
REV. 1.3, NOV. 13, 2013
MX25V512E
HARDWARE FEATURES
•
SCLK Input
• SI/SIO0
- Serial Data Input or Serial Data Output for Dual output mode
• SO/SIO1
- Serial Data Output or Serial Data Output for Dual output mode
• WP# pin
- Hardware write protection
• HOLD# pin
- pause the chip without diselecting the chip
• PACKAGE
- 8-USON (2x3mm)
- 8-pin TSSOP (173mil)
- 8-pin SOP (150mil)
-
All devices are RoHS compliant and Halogen-free
-
Serial clock input
GENERAL DESCRIPTION
MX25V512E is a CMOS 524,288 bit serial Flash memory, which is configured as 65,536 x 8 internally. MX25V512E
features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus
signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device
is enabled by CS# input.
MX25V512E provides sequential read operation on whole chip.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci-
fied page or sector/block locations will be executed. Program command is executed on page (256 bytes) basis, and
erase command is executed on chip or sector (4K-bytes).
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via the WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 25uA DC cur-
rent.
The MX25V512E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
P/N: PM1734
5
REV. 1.3, NOV. 13, 2013
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参数对比
与MX25V512EOI13G相近的元器件有：MX25V512E、MX25V512EZUI13G。描述及对比如下：
型号 MX25V512EOI13G MX25V512E MX25V512EZUI13G
描述 512K-BIT [x 1/x 2] CMOS SERIAL FLASH 512K-BIT [x 1/x 2] CMOS SERIAL FLASH 512K-BIT [x 1/x 2] CMOS SERIAL FLASH
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器件捷径:
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