Data Sheet
Five Output Universal PMIC
MxL7704
General Description
The
MxL7704
is a five output Universal PMIC optimized for
powering low power FPGAs, DSPs, and microprocessors
from 5V inputs. Four synchronous step down buck
regulators range from 1.5A system power to 4A core
power. A 100mA LDO provides a clean 1.5V to 3.6V
power for auxiliary devices. All outputs support ±10%
margining and the two highest power outputs support
dynamic voltage control to support processors that can
utilize this function to save power. Through a 400kHz I
2
C
interface, the customer can monitor an input voltage flag
and PGOOD flags for each output. The I
2
C port can also
be used to modify power up and down sequencing options,
assign PGOOD outputs to the PGOOD pins, enable
outputs and select switching frequency.
High switching frequency and a current mode architecture
with internal compensation enable a very fast transient
response to line and load changes without sacrificing
stability and keeping board space to a minimum.
Fault protection features include input undervoltage
lockout, overcurrent protection, and thermal protection.
The MxL7704 is offered in a 5mm x 5mm QFN package.
Two pre-programmed standard products are available.
The MxL7704-X has been optimized for powering the
Xilinx
®
Zynq
®
Ultrascale+™ ZU2 and ZU3 MPSoCs.
The bucks are pre-programmed to provide the core rail
(0.85V up to 4A), DDR3L memory power (1.35V), I/O and
system power (1.8V and 3.3V). Sequencing is tailored
to the unique needs of the ZU2 and ZU3 MPSoCs,
offering accelerated time to market with Xilinx
®
Zynq
®
Ultrascale+™ ZU2 and ZU3 devices. The MxL7704-A
is designed to power a wide range of ARM
®
Cortex
®
-
based processors (A7, A9, and A53) which use a more
conventional sequencing scheme where the I/O rails
power up first and core is last. The bucks provide the 1.2V
core rail, 1.35V DDR3L power, 1.8V and 3.3V rails for I/O
and system power. VTT is supported by the addition of
the XRP2997 DDR Bus Termination Regulator.
Features
■■
■■
Input voltage range: 4.0V to 5.5V
4 Synchronous Buck Regulators
–
–
–
–
–
–
■■
■■
Internally compensated current mode
1MHz to 2.1MHz switching frequency
Buck 1: 3.0V to 3.6V, 20mV step, 1.5A
Buck 2: 1.3V to 1.92V, 20mV step, 1.5A
Buck 3: 0.8V to 1.6V, 6.25mV step, 2.5A
Buck 4: 0.6V to 1.4V, 6.25mV step, 4A
■■
100mA LDO 1.5V to 3.6V, 20mV step
±2% maximum total dc output error over line, load and
temperature
3.3V/5V 400kHz I
2
C interface
–
Dynamic voltage scaling
–
–
–
■■
Status monitoring by channel
Sequencing control
Input voltage status register
■■
■■
■■
■■
Highly flexible conditional sequencing engine with
external input
2 configurable PGOOD outputs
Adjustable switching frequency
5mm x 5mm 32-pin QFN package
Two standard factory programmed devices
–
MxL7704-A: IO rails up first, core last (1.2V)
–
MxL7704-X for Xilinx
©
ZU2 and ZU3 MPSoCs
Applications
■■
■■
■■
■■
Low power processor, ASIC and FPGA power
Industrial control
Test equipment
POS terminals
Ordering Information -
Back Page
•
www.maxlinear.com
•
Rev 1B
REV1A
i/i
MxL7704 Data Sheet
Revision History
Revision History
Revision
1A
Release Date
2/28/18
Change Description
Initial Release
Added inductor value calculation to Minimum Effective C
OUT
section.
Updated Output Voltage Scaling and I
2
C Operation sections and
Register Descriptions 0x10 - 0x14. Updated ESD table.
Added open drain to PG pin descriptions. Added sentence to PGOOD
section and deleted sentence from Operations section about
unassigned PG pin. Updated General Description and Features with -A
and -X information.
1B
7/3/18
7/3/18
Rev 1B
ii
MxL7704 Data Sheet
Table of Contents
Table of Contents
General Description .................................................................................................................... i
Features........................................................................................................................................ i
Applications ................................................................................................................................. i
MxL7704 Specifications
............................................................................................................. 1
Absolute Maximum Ratings .............................................................................................. 1
ESD Rating .......................................................................................................................... 1
Operating Conditions ......................................................................................................... 1
Electrical Characteristics ................................................................................................... 2
Pin Information ........................................................................................................................... 9
Pin Configuration
............................................................................................................... 9
Pin Description ................................................................................................................. 10
Typical Performance Characteristics ..................................................................................... 11
Functional Block Diagram ....................................................................................................... 14
Applications Information ......................................................................................................... 15
Operation ........................................................................................................................... 15
Output Voltage Scaling .................................................................................................... 15
Sequencing ....................................................................................................................... 16
Power Down Sequencing of Channels ........................................................................... 16
SEQ EN and Channel Enable Bits ................................................................................... 17
Changing Sequencing Registers While Operating ........................................................ 17
PGOOD .............................................................................................................................. 18
Input Voltage Monitor Flag............................................................................................... 18
Hot Start ............................................................................................................................ 18
Sequencing Examples ..................................................................................................... 20
Faults ................................................................................................................................. 22
UVP (Under Voltage Protection) ............................................................................................. 22
OVP (Output Over Voltage Protection) ................................................................................... 22
OCP (Over Current Protection) ............................................................................................... 22
Channel vs Chip Fault Actions ................................................................................................ 23
Minimum t
ON
and Minimum Duty Cycle Limitation ....................................................... 24
7/3/18
Rev 1B
iii
MxL7704 Data Sheet
Table of Contents
Table of Contents
Minimum Effective C
OUT
.................................................................................................. 25
Dynamic Voltage Scaling (DVS) ...................................................................................... 26
Analog to Digital Converter and Temperature Sensor
.................................................. 26
Typical Applications ......................................................................................................... 27
Register Information ........................................................................................................ 29
Slave I
2
C Address .................................................................................................................. 29
Register Map ........................................................................................................................... 29
Default Values ......................................................................................................................... 30
Register Descriptions .............................................................................................................. 31
Mechanical Dimensions ........................................................................................................... 35
Recommended Land Pattern and Stencil............................................................................... 36
Ordering Information................................................................................................................ 37
7/3/18
Rev 1B
iv
MxL7704 Data Sheet
List of Tables
List of Tables
Table 1:
Absolute Maximum Ratings ............................................................................................ 1
Table 2:
ESD Rating ..................................................................................................................... 1
Table 3:
Operating Conditions ...................................................................................................... 1
Table 4:
Electrical Characteristics................................................................................................. 2
Table 5:
Pin Names and Descriptions......................................................................................... 10
Table 6:
Minimum Permissible V
OUT
.......................................................................................... 24
Table 7:
MxL7704-AQB Recommended L and C
OUT
................................................................. 25
Table 8:
MxL7704-XQB Recommended L and C
OUT
................................................................. 25
Table 9:
Register Map................................................................................................................. 29
Table 10:
Default Values ............................................................................................................. 30
Table 11:
Ordering Information ................................................................................................... 37
7/3/18
Rev 1B
v
FPGA/CPLD
