N16D1633LPAW
512K
x
16Bits
x
2Banks Low Power Synchronous DRAM
Description
These N16D1633LPAW are low power 16,777,216 bits CMOS Synchronous DRAM organized as 2 banks of 524,288 words x 16 bits.
These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input
and output voltage levels are compatible with LVCMOS.
Features
JEDEC standard 3.0V/3.3V power supply.
• Auto refresh and self refresh.
• All pins are compatible with LVCMOS interface.
• 4K refresh cycle / 64ms.
• Programmable Burst Length and Burst Type.
- 1, 2, 4, 8 or Full Page for Sequential Burst.
- 4 or 8 for Interleave Burst.
• Programmable CAS Latency : 2,3 clocks.
• Programmable Driver Strength Control
- Full Strength or 1/2, 1/4 of Full Strength
• Deep Power Down Mode.
• All inputs and outputs referenced to the positive edge of the
system clock.
• Data mask function by DQM.
• Internal dual banks operation.
• Burst Read Single Write operation.
• Special Function Support.
- PASR(Partial Array Self Refresh)
- Auto TCSR(Temperature Compensated Self Refresh)
• Automatic precharge, includes CONCURRENT Auto Precharge
Mode and controlled Precharge.
Table1: Ordering Information
Part No.
N16D1633LPAW-75I
Clock Freq.
133 MHz
Temperature
-25°C to 85°C
VDD/VDDQ
3.0V/3.0V
or
3.3V/3.3V
Interface
LVCMOS
Package
Wafer
Ver. A
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N16D1633LPAW
Figure1: Known Good Die Configuration (Top View)
Double-Side Bond Pad
•
•
•
KGD
•
•
•
Table2: Pin Descriptions
Pin
CLK
Pin Name
System Clock
Descriptions
The system clock input. All other inputs are registered to the
SDRAM on the rising edge CLK.
Controls internal clock signal and when deactivated, the SDRAM
will be one of the states among power down, suspend or self
refresh.
Enable or disable all inputs except CLK, CKE and DQM.
Selects bank to be activated during RAS activity.
Selects bank to be read/written during CAS activity.
Row Address
Column Address
Auto Precharge
: RA0~RA10
: CA0~CA7
: A10
CKE
/CS
A11
Clock Enable
Chip Select
Bank Address
A0~A10
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
/RAS, /CAS, /WE
RAS, CAS and WE define the operation.
Refer function truth table for details.
Controls output buffers in read mode and masks input data in
write mode.
Multiplexed data input/output pin.
Power supply for internal circuits and input buffers.
Power supply for output buffers.
No connection.
LDQM/UDQM
DQ0~DQ15
VDD/VSS
VDDQ/VSSQ
NC
Ver. A
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N16D1633LPAW
Figure2: Functional Block Diagram
EXTENDED
MODE
REGISTER
CLOCK
GENERATOR
TCSR
PASR
CLK
CKE
ADDRESS
ROW
MODE
REGISTER
ADDRESS
BUFFER &
REFRESH
COUNTER
BANK B
BANK A
ROW DECODER
ROW DECODER
SENSE AMPLIFIER
/CS
/RAS
/CAS
/WE
COLUMN DECODER
COLUMN
ADDRESS
BUFFER &
BURST
COUNTER
DATA CONTROL CIRCUIT
COMMAND DECODER
CONTROL LOGIC
& LATCH CIRCUIT
DQM
LATCH CIRCUIT
INPUT & OUTPUT
BUFFER
DQ
Ver. A
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N16D1633LPAW
Figure3: Simplified State Diagram
EXTENDED
MODE
REGISTER
SET
EM
RS
SELF
REFRESH
LF
SE
XI
FE
EL
S
T
MODE
REGISTER
SET
MRS
IDLE
CK
E
D
DP
IT
EX
REF
CBR
REFRESH
CK
E
↓
ACT
DEEP
POWER
DOWN
D
DP
POWER
DOWN
ROW
ACTIVE
T
BS
CKE
↓
CKE
BS
T
ACTIVE
POWER
DOWN
E
RG
HA
EC
PR
H
IT
TO
AU
ITE W
WR
PRE
W
AU
RIT
TO
E
PR
WIT
EC
H
HA
RG
E
WRITE
READ
WRITE
SUSPEND
CKE
↓
WRITE
CKE
READ
CKE
↓
READ
CKE
READ
SUSPEND
WRITE
WRITE A
SUSPEND
CKE
↓
WRITE A
atio
n)
CKE
↓
READ A
CKE
E
PR
READ A
SUSPEND
CKE
POWER
ON
PRECHARGE
PRE-
CHARGE
PR
E(P
rec
h
arg
e
e
arg
ech
(Pr
n)
atio
min
ter
ter
min
Automatic Sequence
Manual Input
Ver. A
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Figure4: Mode Register Definition
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
N16D1633LPAW
Address Bus
11
0
10
0
9
WB
0
8
0
7
6
5
4
BT
3
2
1
0
Mode Register (Mx)
CAS Latency
Burst Length
M9
0
1
Write Burst Mode
Burst Read and Burst Write
Burst Read and Single Write
M6
0
0
0
0
1
1
1
1
M5
0
0
1
1
0
0
1
1
M4
0
1
0
1
0
1
0
1
CAS Latency
Reserved
1
2
3
Reserved
Reserved
Reserved
Reserved
M3
0
1
Burst Type
Sequential
Interleave
M2
0
0
0
0
1
1
1
1
M1
0
0
1
1
0
0
1
1
M0
0
1
0
1
0
1
0
1
Burst Length
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Note: M11(A11) must be set to “0” to select Mode Register (vs. the Extended Mode Register)
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is
selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column
address, as shown in Table 3.
Table 3: Burst Definition
Burst
Length
2
0
4
0
1
1
0
0
0
8
0
1
1
1
1
Full
Page
0
0
1
1
0
0
1
1
n=A0-7
(Location 0-256)
Starting Column Order of Access Within a Burst
Address
Sequential
Interleaved
A2
A1 A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
C
n
, C
n
+1. C
n
+2,
C
n
+3, C
n
+4…
…C
n
-1, C
n
...
Not Supported
0-1
1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Note :
1. For full-page accesses: y = 256
2. For a burst length of two, A1-A7 select the block-
of-two burst; A0 selects the starting column within the
block.
3. For a burst length of four, A2-A7 select the block-
of-four burst; A0-A1 select the starting column within
the block.
4. For a burst length of eight, A3-A7 select the
block-of-eight burst; A0-A2 select the starting column
within the block.
5. For a full-page burst, the full row is selected and A0-A7
select the starting column.
6. Whenever a boundary of the block is reached within a
given sequence above, the following access wraps
within the block.
7. For a burst length of one, A0-A7 select the unique
column to be accessed, and mode register bit M3 is
ignored.
Ver. A
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