NB2308A
3.3 V Zero Delay
Clock Buffer
The NB2308A is a versatile, 3.3 V zero delay buffer designed to
distribute high-
-speed clocks. It is available in a 16 pin package. The
part has an on-
-chip PLL which locks to an input clock presented on
the REF pin. The PLL feedback is required to be driven to FBK pin,
and can be obtained from one of the outputs. The input- -output
-to-
propagation delay is guaranteed to be less than 250 ps, and the
output- -output skew is guaranteed to be less than 200 ps.
-to-
The NB2308A has two banks of four outputs each, which can be
controlled by the select inputs as shown in the Select Input Decoding
Table. If all the output clocks are not required, Bank B can be
three-
-stated. The select input also allows the input clock to be directly
applied to the outputs for chip and system testing purposes.
Multiple NB2308A devices can accept the same input clock and
distribute it. In this case the skew between the outputs of the two
devices is guaranteed to be less than 700 ps.
The NB2308A is available in five different configurations (Refer to
NB2308A Configurations Table). The NB2308AI1 is the base part,
where the output frequencies equal the reference if there is no counter
in the feedback path. The NB2308AI1H is the high-
-drive version of
the - and the rise and fall times on this device are much faster.
-1
The NB2308AI2 allows the user to obtain 2X and 1X frequencies on
each output bank. The exact configuration and output frequencies
depends on which output drives the feedback pin. The NB2308AI3
allows the user to obtain 4X and 2X frequencies on the outputs.
The NB2308AI4 enables the user to obtain 2X clocks on all outputs.
Thus, the part is extremely versatile, and can be used in a variety of
applications.
The NB2308AI5H is a high-
-drive version with REF/2 on both
banks.
Features
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MARKING
DIAGRAMS*
16
1
SOIC-
-16
D SUFFIX
CASE 751B
1
XXXXXXXXXG
AWLYWW
16
16
16
1
TSSOP-
-16
DT SUFFIX
CASE 948F
1
XXXX
XXXX
ALYWG
G
XXXX = Device Code
A
= Assembly Location
WL, L = Wafer Lot
Y
= Year
WW, W = Work Week
G or
G
= Pb--Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Zero Input -- Output Propagation Delay, Adjustable by Capacitive
Load on FBK Input
Multiple Configurations - Refer to NB2308A Configurations Table
-
Input Frequency Range: 15 MHz to 133 MHz
Multiple Low-
-Skew Outputs
Output-
-Output Skew Less than 200 ps
Device-
-Device Skew Less than 700 ps
Two banks of four outputs, three-
-stateable by two select inputs
Less than 200 ps Cycle- -Cycle Jitter
-to-
Available in 16-
-pin SOIC and TSSOP Packages
3.3 V Operation
Guaranteed Across Commercial and Industrial Temperature Ranges
Advanced 0.35
m
CMOS Technology
These are Pb-
-Free Devices
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Semiconductor Components Industries, LLC, 2010
October, 2010 - Rev. 8
-
1
Publication Order Number:
NB2308A/D
NB2308A
FBK
PLL
CLKA1
MUX
Extra Divider (--5H)
CLKA2
÷2
REF
÷2
Extra Divider (--3, --4)
CLKA3
S2
SELECT INPUT
DECODING
S1
÷2
CLKA4
CLKB1
Extra Divider (--2, --3)
CLKB2
CLKB3
CLKB4
Figure 1. Block Diagram
(see Figures 11, 12, 13, 14 and 15 for device specific Block Diagrams)
Table 1. CONFIGURATIONS
Device
NB2308AI1
NB2308AI1H
NB2308AI2
NB2308AI2
NB2308AI3
NB2308AI3
NB2308AI4
NB2308AI5H
Feedback From
Bank A or Bank B
Bank A or Bank B
Bank A
Bank B
Bank A
Bank B
Bank A or Bank B
Bank A or Bank B
Bank A Frequency
Reference
Reference
Reference
2 X Reference
2 X Reference
4 X Reference
2 X Reference
Reference
÷2
Reference
Reference
Reference
÷2
Reference
Reference or Reference (Note 1)
2 X Reference
2 X Reference
Reference
÷2
Bank B Frequency
1. Output phase is indeterminant (0 or 180 from input clock). If phase integrity is required, use the NB2308AI2.
Table 2. SELECT INPUT DECODING
S2
0
0
1
1
S1
0
1
0
1
Clock A1 - A4
-
Three--state
Driven
Driven (Note 2)
Driven
Clock B1 - B4
-
Three--state
Three--state
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL ShutDown
Y
N
Y
N
2. Outputs inverted on 2308--2 and 2308--3 in bypass mode, S2 = 1 and S1 = 0.
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2
NB2308A
REF
CLKA1
CLKA2
1
2
3
4
16
15
14
13
FBK
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
V
DD
GND
NB2308A
5
6
7
8
12
11
10
9
CLKB1
CLKB2
S2
Figure 2. Pin Configuration
Table 3. PIN DESCRIPTION
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
REF (Note 3)
CLKA1 (Note 4)
CLKA2 (Note 4)
V
DD
GND
CLKB1 (Note 4)
CLKB2 (Note 4)
S2 (Note 5)
S1 (Note 5)
CLKB3 (Note 4)
CLKB4 (Note 4)
GND
V
DD
CLKA3 (Note 4)
CLKA4 (Note 4)
FBK
Description
Input reference frequency, 5 V tolerant input.
Buffered clock output, Bank A.
Buffered clock output, Bank A.
3.3 V supply.
Ground.
Buffered clock output, Bank B.
Buffered clock output, Bank B.
Select input, bit 2.
Select input, bit 1.
Buffered clock output, Bank B.
Buffered clock output, Bank B.
Ground.
3.3 V supply.
Buffered clock output, Bank A.
Buffered clock output, Bank A.
PLL feedback input.
3. Weak pulldown.
4. Weak pulldown on all outputs.
5. Weak pullup on these inputs.
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3
NB2308A
Table 4. MAXIMUM RATINGS
Parameter
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
DC Input Voltage (REF)
Storage Temperature
Maximum Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (per MIL--STD--883, Method 3015)
Min
--0.5
--0.5
--0.5
--65
Max
+7.0
V
DD
+ 0.5
7
+150
260
150
>2000
Unit
V
V
V
C
C
C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 5. OPERATING CONDITIONS
Parameter
V
DD
T
A
C
L
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance (Note 6)
Industrial
Commercial
Description
Min
3.0
--40
0
Max
3.6
85
70
30
15
7
Unit
V
C
pF
pF
pF
6. Applies to both REF Clock and FBK.
Table 6. ELECTRICAL CHARACTERISTICS
V
CC
= 3.0 V to 3.6 V, GND = 0 V, T
A
= --40C to +85C
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Voltage
Output HIGH Voltage
Supply Current (Note 7)
V
IN
= 0 V
V
IN
= V
DD
I
OL
= 8 mA (--1, --2, --3, --4)
I
OL
= 12 mA (--1H, --5H)
I
OH
= --8 mA (--1, --2, --3, --4)
I
OH
= --12 mA (--1H, --5H)
Unloaded outputs 100 MHz REF
Select inputs at V
DD
or GND
Unloaded outputs, 66 MHz REF
(--1, --2, --3, --4)
Unloaded outputs, 33 MHz REF
(--1, --2, --3, --4)
7. Supply currents are measured for PLL--Bypass Mode (S2 = 1, S1 = 0).
--2, --3, --4
--1H, --5H
2.4
49
60
34
18
2.0
50.0
100.0
0.4
Test Conditions
Min
Max
0.8
Unit
V
V
mA
mA
V
V
mA
mA
mA
mA
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4
NB2308A
Table 7. SWITCHING CHARACTERISTICS
V
CC
= 3.0 V to 3.6 V, GND = 0 V, T
A
= --40C to +85C
Parameter
t
1
Description
Output Frequency
Test Conditions
30 pF load (all devices)
15 pF load (--1H, --5H)
15 pF load (--1, --2, --3, --4)
Measured at 1.4 V, F
OUT
= < 66.66 MHz
30 pF load
Measured at 1.4 V, F
OUT
= < 50 MHz
15 pF load
t
3
Output Rise Time
(--1, --2, --3, --4)
Measured between 0.8 V and 2.0 V
30 pF load
Measured between 0.8 V and 2.0 V
15 pF load
Output Rise Time
(--1H, --5H)
t
4
Output Fall Time
(--1, --2, --3, --4)
Measured between 0.8 V and 2.0 V
30 pF load
Measured between 2.0 V and 0.8 V
30 pF load
Measured between 0.8 V and 2.0 V
15 pF load
Output Fall Time
(--1H, --5H)
t
5
Output--to--Output Skew on same Bank
(--1, --2, --3, --4)
Output--to--Output Skew
(--1H, --5H)
Output Bank A--to--Output Bank B Skew
(--1, --4, --5H)
Output Bank A--to--Output Bank B Skew
(--2, --3)
t
6
t
7
t
J
Delay, REF Rising Edge to FBK
Rising Edge
Device--to--Device Skew
Cycle--to--Cycle Jitter
(--1, --1H, --4, --5H)
Measured between 2.0 V and 0.8 V
30 pF load
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on the FBK pins of the
device
Measured at 66.67 MHz, loaded outputs,
15 pF load
Measured at 66.67 MHz, loaded outputs,
30 pF load
Measured at 133.3 MHz, loaded outputs
15 pF load
Cycle--to--Cycle Jitter
(--2, --3)
Measured at 66.67 MHz, loaded outputs,
30 pF load
Measured at 66.67 MHz, loaded outputs,
15 pF load
t
LOCK
PLL Lock Time
Stable power supply, valid clock presented
on REF and FBK pins
0
0
Min
15
15
15
40.0
45.0
50.0
50.0
Typ
Max
100
133.3
133.3
60.0
55.0
2.20
1.50
1.50
2.20
1.50
1.25
200
200
200
400
250
700
200
200
100
400
400
1.0
ms
ps
ps
ps
ps
ns
ns
Unit
MHz
t
1
Duty Cycle = (t
2
/ t
1
) * 100
(all devices)
%
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