NB3U23C
1.2 V Dual Channel CMOS
Buffer / Translator
Description
The NB3U23C is a 2−input, 2−output buffer/voltage translator for
UFS (Universal Flash Storage) in portable consumer applications such
as mobile phones, tablets, cameras, etc. This dual channel CMOS
buffer accepts 1.8 V CMOS input and translates it to 1.2 V CMOS
output. The device is powered using single supply of 1.2 V
±5%.
The NB3U23C is packaged in 2 ultra−small 6−pin packages: the 6
pin SC70 and a 6 pin thin UDFN package.
Features
http://onsemi.com
MARKING
DIAGRAMS
6
SC−70
SQ SUFFIX
CASE 419B
1
23C
= Device Code
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
UDFN6
MN SUFFIX
CASE 517CW
C
M
= Device Code
= Date Code
23CMG
G
•
•
•
•
•
•
1
Operating Frequency: 52 MHz (Max)
Propagation Delay: 5 ns (Max)
Low Standby Current: < 10
mA
at 1.2 V V
DD
Low Phase Noise Floor: −150 dBc/Hz (Typ)
Rise/Fall Times (tr/tf): 2 ns (Max)
ESD Protection Exceeds JEDEC Standards
♦
2000 V Human−Body Model (JS−001−2012)
♦
200 V Machine Model (JESD22−A115C)
♦
1000 V Charged−Device Model (JESDC101E)
•
Operating Supply Voltage Range (V
DD
): 1.2 V
±5%
•
Operating Temperature Range (Industrial): −40°C to 85°C
•
These are Pb−Free Devices
CM
VDD
5
IN1
1
1
6
OUT1
IN2
3
2
2
4
OUT2
GND
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 4 of
this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
April, 2014 − Rev. 6
Publication Order Number:
NB3U23C/D
NB3U23C
IN1
IN1
1
6
OUT1
GND
GND
2
SC70−6
Package
5
VDD
IN2
IN2
3
4
OUT2
3
UDFN6
Package
4
OUT2
2
5
VDD
1
6
OUT1
Figure 2. Pinout Diagram
(Top Views)
Table 1. PIN DESCRIPTION
Number
1
2
3
4
5
6
Name
IN1
GND
IN2
OUT2
VDD
OUT1
Input Clock Signal − Channel 1
Power Supply Ground (0 V)
Input Clock Signal − Channel 2
Output − Channel 2
Power Supply Voltage
Output − Channel 1
Description
Table 2. ATTRIBUTES
Characteristic
ESD Protection
Human Body Model
Machine Model
Charge Device Model
Value
2 kV min
200 V min
1 kV min
Level 1
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
120
Moisture Sensitivity (Note 1)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test II
1. For additional information, see Application Note AND8003/D.
http://onsemi.com
2
NB3U23C
Table 3. MAXIMUM RATINGS
(Note 2)
Symbol
V
DD
V
in
I
D
T
A
T
stg
q
JA
Supply Voltage
Input Voltage
Output Current
Operating Temperature Range, Industrial
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm (Note 3)
0 lfpm
500 lfpm (Note 3)
(Note 3)
SC70−6
UDFN−6
SC70−6
UDFN−6
Parameter
Condition 1
Condition 2
Rating
3.6
–0.5
≤
V
I
≤
2.5
25
−40 to +85
−65 to +150
210
126
245
172
100
150
260
Unit
V
V
mA
°C
°C
°C/W
q
JC
T
sol
Thermal Resistance (Junction−to−Case)
Wave Solder
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If
stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
Table 4. ELECTRICAL CHARACTERISTICS
(VDD = 1.2
±5%
V, GND = 0 V, T
A
= −40°C to +85°C)
Symbol
DIDD
Characteristic
Power Supply Current
(Single Channel Switching @ 52 MHz)
Power Supply Current
(Both Channels Switching @ 52 MHz)
I
off
V
IH
V
IL
V
OH
V
OL
C
in
F
clk
t
PD
Standby Current
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Capacitance
Operating Frequency Range
Propagation Delay
Phase Noise Floor Density
(Notes 4 and 5)
Additive RMS Phase Jitter
(Notes 5 and 6)
INx to OUTx
C
L
= 20 pF, R
L
= 100 kW
C
L
= 20 pF
R
L
= 100 kW
C
L
= 20 pF
R
L
= 100 kW
Offset Frequency Range:
50 kHz to 10 MHz
Input Duty Cycle = 50%,
Min Input Slew Rate = 1 V/ns
0.2 * V
DD
to 0.8 * VDD
C
L
= 20 pF
R
L
= 100 kW
45
−150
0.15
0.25
0
C
L
= 20 pF
R
L
= 100 kW
C
L
= 20 pF
R
L
= 100 kW
Conditions
C
L
= 20 pF
C
L
= 5 pF
C
L
= 1 pF
C
L
= 20 pF
C
L
= 5 pF
C
L
= 1 pF
Vi = V
IH
Max or GND;
V
DD
= 1.2 V, No Output Load
0.65 * VDD
0
0.75 * VDD
0
Min
Typ
2.5
1.5
1
5
3
2
10
1.98
0.35 * VDD
VDD
0.25 * VDD
5
52
5
Max
Unit
mA
mA
mA
V
V
V
V
pF
MHz
ns
dBc/Hz
ps
DC
tr/tf
Output Duty Cycle (Note 7)
Output Rise/Fall Times
55
2
%
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. White noise floor.
5. This parameter refers to the random jitter only.
6. The output RMS phase jitter can be calculated using the following equation:
(Output RMS Phase Jitter)
2
= (Input RMS Phase Jitter)
2
+ (Additive RMS Phase Jitter)
2
7. Measured with input voltage swing from 0 V to 1.8 V.
http://onsemi.com
3
NB3U23C
INx
C
L
= 20 pF
OUTx
R
L
= 100 kW
GND
Figure 3. Typical Test Setup for Evaluation
0
−20
−40
POWER (dBc/Hz)
−60
−80
−100
−120
−140
−160
−180
1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07
OFFSET FREQUENCY (Hz)
Figure 4. Typical Phase Noise Plot at 50 MHz Carrier Frequency
ORDERING INFORMATION
Device
NB3U23CSQTCG
NB3U23CMNTAG
Package
SC−70−6
(Pb−Free)
UDFN6
(Pb−Free)
Shipping
†
3000 / Tape & Reel
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
4
NB3U23C
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
2X
aaa H D
D
A
D
5
4
H
GAGE
PLANE
6
L2
E
1
2X
2
3
L
DETAIL A
E1
aaa C
bbb H D
2X 3 TIPS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-
SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI-
TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
DIM
A
A1
A2
b
C
D
E
E1
e
L
L2
aaa
bbb
ccc
ddd
MILLIMETERS
MIN
NOM MAX
−−−
−−−
1.10
0.00
−−−
0.10
0.70
0.90
1.00
0.15
0.20
0.25
0.08
0.15
0.22
1.80
2.00
2.20
2.00
2.10
2.20
1.15
1.25
1.35
0.65 BSC
0.26
0.36
0.46
0.15 BSC
0.15
0.30
0.10
0.10
INCHES
NOM MAX
−−− 0.043
−−− 0.004
0.035 0.039
0.008 0.010
0.006 0.009
0.078 0.086
0.082 0.086
0.049 0.053
0.026 BSC
0.010 0.014 0.018
0.006 BSC
0.006
0.012
0.004
0.004
MIN
−−−
0.000
0.027
0.006
0.003
0.070
0.078
0.045
e
B
TOP VIEW
6X
b
ddd
M
C A-B D
A2
A
DETAIL A
6X
ccc C
SIDE VIEW
A1
C
SEATING
PLANE
c
END VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.30
6X
0.66
2.50
0.65
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
5
