D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
NC7SP17 — TinyLogic
®
ULP Single Buffer with Schmitt Trigger Input
November 2010
NC7SP17
TinyLogic
®
ULP Single Buffer with Schmitt Trigger Input
Features
0.9V to 3.6V V
CC
Supply Operation
3.6V Over-Voltage Tolerant I/Os at V
CC
from
0.9V to 3.6V
Propagation Delay (t
PD
):
4.0ns Typical for 3.0V to 3.6V V
CC
5.0ns Typical for 2.3V to 2.7V V
CC
6.0ns Typical for 1.65V to 1.95V V
CC
7.0ns Typical for 1.40V to 1.60V V
CC
11.0ns Typical for 1.10V to 1.30V V
CC
27.0ns Typical for 0.90V V
CC
Power-Off High-Impedance Inputs and Outputs
Static Drive (I
OH
/I
OL
):
± 2.6mA at 3.00V V
CC
± 2.1mA at 2.30V V
CC
± 1.5mA at 1.65V V
CC
± 1.0mA at 1.40V V
CC
± 0.5mA at 1.10V V
CC
± 20µA at 0.9V V
CC
Quiet Series™ Noise / EMI Reduction Circuitry
Ultra Small MicroPak™ Packages
Ultra Low Dynamic Power
Description
The NC7SP17 is a single buffer with Schmitt trigger
input from Fairchild’s Ultra Low Power (ULP) series of
TinyLogic®. Ideal for applications where battery life is
critical, this product is designed for ultra low power
consumption within the V
CC
operating range of 0.9V to
3.6V V
CC
.
The internal circuit is composed of a minimum of
inverter stages, including the output buffer, to enable
ultra low static and dynamic power.
The NC7SP17, for lower drive requirements, is uniquely
designed for optimized power and speed and is
fabricated with an advanced CMOS technology to
achieve best-in-class speed of operation, while
maintaining extremely low CMOS power dissipation.
Ordering Information
Part Number
NC7SP17P5X
NC7SP17L6X
NC7SP17FHX
(Preliminary)
Top Mark
P17
K4
K4
Package
5-Lead SC70, EIAJ SC-88a, 1.25mm Wide
6-Lead MicroPak™, 1.00mm Wide
6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch
Packing Method
3000 Units on Tape & Reel
5000 Units on Tape & Reel
5000 Units on Tape & Reel
© 2001 Fairchild Semiconductor Corporation
NC7SP17 • Rev. 1.0.3
www.fairchildsemi.com
NC7SP17 — TinyLogic
®
ULP Single Buffer with Schmitt Trigger Input
Notes:
1. TinyLogic ULP and ULP-A with up to 50% less power
consumption can extend battery life significantly.
2. Battery Life=(V
battery
x I
battery
x 0.9) / (P
device
) /
24hrs/day; where, P
device
=(I
CC
x V
CC
) + (C
PD
+ C
L
)
2
x V
CC
x f.
3. Assumes ideal 3.6V Lithium Ion battery with current
rating of 900mAH and derated 90% and device
frequency at 10MHz, with C
L
=15pF load.
Figure 1. Battery Life vs. V
CC
Supply Voltage
Connection Diagrams
IEEE/IEC
A
1
Figure 2. Logic Symbol
Y
Pin Configurations
NC
A
GND
1
5
V
CC
NC
A
1
2
3
6
5
4
V
CC
NC
Y
2
3
4
Y
GND
Figure 3. SC70 (Top View)
Figure 4. MicroPak™ (Top Through View)
Function Table
Y=A
Input
A
L
H
L = Low Logic Level
H = High Logic Level
Output
Y
L
H
Pin Definitions
Pin # SC70
1
2
3
4
5
Pin # MicroPak
1, 5
2
3
4
6
Name
NC
A
GND
Y
V
CC
Input
Description
No Connect
Ground
Output
Supply Voltage
© 2001 Fairchild Semiconductor Corporation
NC7SP17 • Rev. 1.0.3
www.fairchildsemi.com
2
NC7SP17 — TinyLogic
®
ULP Single Buffer with Schmitt Trigger Input
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OH
/ I
OL
T
STG
T
J
T
L
P
D
Supply Voltage
DC Input Voltage
DC Output Voltage
Parameter
Min.
-0.5
-0.5
Max.
4.6
4.6
V
CC
to +0.5
4.6
-50
-50
+50
±50
±50
Unit
V
V
V
V
mA
mA
mA
mA
°C
°C
°C
mW
HIGH or LOW State
V
CC
=0V
V
OUT
< 0V
V
OUT
> V
CC
(4)
-0.5
-0.5
DC Input Diode Current at V
IN
< 0V
DC Output Diode Current
DC Output Source/Sink Current
Storage Temperature Range
Junction Temperature Under Bias
Junction Lead Temperature (Soldering, 10 Seconds)
SC70-5
Power Dissipation at +85°C
Human Body Model
Charged Device Model
MicroPak™-6
MicroPak2™-6
JEDEC: JESD22-A114
JEDEC: JESD22-C101
-65
I
CC
or Ground DC V
CC
or Ground Current per Supply Pin
+150
+150
+260
150
130
120
4000
2000
ESD
V
Note:
4. The I
O
maximum rating must be observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
V
CC
V
IN
V
OUT
Parameter
Supply Voltage
Input Voltage
(5)
Conditions
Min.
0.9
0
Typ.
Max.
3.6
3.6
V
CC
3.6
Unit
V
V
V
Output Voltage
HIGH or LOW State
V
CC
=0V
V
CC
=3.0V to 3.6V
V
CC
=2.3V to 2.7V
V
CC
=1.65V to 1.95V
V
CC
=1.40V to 1.60V
V
CC
=1.10V to 1.30V
V
CC
=0.9V
0
0
±2.6
±2.1
±1.5
±1.0
±0.5
20.0
-40
I
OH
/ I
OL
Output Current in I
OH
/ I
OL
mA
µA
+85
°C
ns/V
°C/W
T
A
Δt
/
ΔV
θ
JA
Free Air Operating Temperature
Minimum Input Edge Rate
Thermal Resistance
V
IN
=0.8V to 2.0V, V
CC
=3.0V
SC70-5
MicroPak™-6
MicroPak2™-6
10
425
500
560
Note:
5. Unused inputs must be held HIGH or LOW. They may not float.
© 2001 Fairchild Semiconductor Corporation
NC7SP17 • Rev. 1.0.3
www.fairchildsemi.com
3
NC7SP17 — TinyLogic
®
ULP Single Buffer with Schmitt Trigger Input
DC Electrical Characteristics
Symbol
Parameter
Conditions
V
CC
(V)
0.90
1.10
V
P
Positive Threshold Voltage
1.40
1.65
2.30
3.00
0.90
1.10
V
N
Negative Threshold Voltage
1.40
1.65
2.30
3.00
0.90
1.10
V
H
Hysteresis Voltage
1.40
1.65
2.30
3.00
0.90
1.10
≤
V
CC
≤
1.30
I
OH
=–20µA
1.40
≤
V
CC
≤
1.60
1.65
≤
V
CC
≤
1.95
2.30
≤
V
CC
≤
2.70
3.00
≤
V
CC
≤
3.60
I
OH
=–0.5mA
I
OH
=–1mA
I
OH
=–1.5mA
I
OH
=–2.1mA
I
OH
=–2.6mA
1.40
≤
V
CC
≤
1.60
1.65
≤
V
CC
≤
1.95
2.30
≤
V
CC
≤
2.70
3.00
≤
V
CC
≤
3.60
0.90
1.10
≤
V
CC
≤
1.30
I
OL
=20µA
1.40
≤
V
CC
≤
1.60
1.65
≤
V
CC
≤
1.95
2.30
≤
V
CC
≤
2.70
V
OL
LOW Level Output
Voltage
I
OL
=0.5mA
I
OL
=1mA
I
OL
=1.5mA
I
OL
=2.1mA
I
OL
=2.6mA
I
IN
I
OFF
I
CC
Input Leakage Current
Power Off Leakage
Current
Quiescent Supply
Current
0
≤
V
IN
≤
3.6V
0
≤
(V
IN
, V
O
)
≤
3.6V
V
IN
=V
CC
or GND
3.00
≤
V
CC
≤
3.60
1.10
≤
V
CC
≤
1.30
1.40
≤
V
CC
≤
1.60
1.65
≤
V
CC
≤
1.95
2.30
≤
V
CC
≤
2.70
3.00
≤
V
CC
≤
3.60
0.90 to 3.60
0
0.90 to 3.60
T
A
=+25°C
Min.
0.30
0.40
0.50
0.70
1.00
1.50
0.10
0.15
0.20
0.25
0.40
0.6
0.07
0.08
0.09
0.10
0.25
0.60
V
CC
– 0.1
V
CC
– 0.1
V
CC
– 0.1
V
CC
– 0.1
V
CC
– 0.1
V
CC
– 0.1
1.07
1.24
1.95
2.61
0.1
0.1
0.1
0.1
0.1
0.1
0.30 x
V
CC
0.31
0.31
0.31
0.31
±0.1
0.5
0.9
T
A
=–40°C to +85°C
Min.
0.30
0.40
0.50
0.70
1.00
1.50
0.10
0.15
0.20
0.25
0.40
0.60
0.07
0.08
0.09
0.10
0.25
0.60
V
CC
– 0.1
V
CC
– 0.1
V
CC
– 0.1
V
CC
– 0.1
V
CC
– 0.1
V
CC
– 0.1
0.70 x V
CC
0.99
1.22
1.87
2.55
0.1
0.1
0.1
0.1
0.1
0.1
0.30 x
V
CC
0.37
0.35
0.33
0.33
±0.5
0.5
0.9
Max.
0.60
1.00
1.20
1.50
1.90
2.60
0.60
0.70
0.80
0.90
1.15
1.50
0.50
0.60
0.80
1.00
1.10
1.80
Max.
0.60
1.00
1.20
1.50
1.90
2.60
0.60
0.70
0.80
0.90
1.15
1.50
0.50
0.60
0.80
1.00
1.10
1.80
Units
V
V
V
V
OH
HIGH Level Output
Voltage
V
1.10
≤
V
CC
≤
1.30 0.75 x V
CC
V
µA
µA
µA
© 2001 Fairchild Semiconductor Corporation
NC7SP17 • Rev. 1.0.3
www.fairchildsemi.com
4
FPGA/CPLD
