Dual-Core Intel
®
Itanium
®
Processor
9000 and 9100 Series
Dual-Core Intel
®
Itanium
®
Processor 1.6 GHz with 24 MB L3 Cache 9050
Dual-Core Intel
®
Itanium
®
Processor 1.6 GHz with 18 MB L3 Cache 9040
Dual-Core Intel
®
Itanium
®
Processor 1.6 GHz with 8 MB L3 Cache 9030
Dual-Core Intel
®
Itanium
®
Processor 1.42 GHz with 12 MB L3 Cache 9020
Dual-Core Intel
®
Itanium
®
Processor 1.4 GHz with 12 MB L3 Cache 9015
Intel
®
Itanium
®
Processor 1.6 GHz with 6 MB L3 Cache 9010
Dual-Core Intel® Itanium® Processor 1.66/1.6 GHz with 24 MB L3 Cache 9152
Dual-Core Intel
®
Itanium
®
Processor 1.66 GHz with 24 MB L3 Cache 9150M
Dual-Core Intel
®
Itanium
®
Processor 1.6 GHz with 24 MB L3 Cache 9150N
Dual-Core Intel
®
Itanium
®
Processor 1.66 GHz with 18 MB L3 Cache 9140M
Dual-Core Intel
®
Itanium
®
Processor 1.6 GHz with 18 MB L3 Cache 9140N
Dual-Core Intel
®
Itanium
®
Processor 1.42 GHz with 12 MB L3 Cache 9120N
Dual-Core Intel
®
Itanium
®
Processor 1.66 GHz with 8 MB L3 Cache 9130M
Intel
®
Itanium
®
Processor 1.6 GHz with 12 MB L3 Cache 9110N
Datasheet
October 2007
Document Number: 314054-002
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®
PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,
BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS
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life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them
The Dual-Core Intel
®
Itanium
®
9000 and 9100 series processor may contain design defects or errors known as errata which may
cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained
by calling1-800-548-4725, or by visiting Intel's website at http://www.intel.com.
Intel, Itanium, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United
States and other countries.
Copyright © 2002-2007, Intel Corporation
*Other names and brands may be claimed as the property of others.
I2C is a two-wire communication bus /protocol developed by Phillips. SMBus is a subset of the I2C bus/protocol developed by Intel.
Implementation of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Phillips
Electronics, N.V. and North American Phillips Corporation.
2
Dual-Core Intel
®
Itanium
®
Processor 9000 and 9100 Series Datasheet
Contents
1
Introduction............................................................................................................... 11
1.1
Overview ......................................................................................................... 11
1.2
Processor Abstraction Layer ................................................................................ 11
1.3
Mixing Processors of Different Frequencies and Cache Sizes .................................... 12
1.4
Terminology ..................................................................................................... 12
1.5
State of Data .................................................................................................... 12
1.6
Reference Documents ........................................................................................ 13
Electrical Specifications ............................................................................................... 15
2.1
Dual-Core Intel
®
Itanium
®
Processor 9000 and 9100 Series System Bus .................. 15
2.1.1
System Bus Power Pins ........................................................................ 15
2.1.2
System Bus No Connect ....................................................................... 15
2.2
System Bus Signals ........................................................................................... 15
2.2.1
Signal Groups ..................................................................................... 15
2.2.2
Signal Descriptions .............................................................................. 17
2.3
Package Specifications ....................................................................................... 18
2.4
Signal Specifications .......................................................................................... 18
2.4.1
Maximum Ratings ................................................................................ 22
2.5
System Bus Signal Quality Specifications and Measurement Guidelines ..................... 23
2.5.1
Overshoot/Undershoot Magnitude .......................................................... 23
2.5.2
Overshoot/Undershoot Pulse Duration .................................................... 24
2.5.3
Activity Factor..................................................................................... 24
2.5.4
Reading Overshoot/Undershoot Specification Tables ................................. 24
2.5.5
Determining if a System Meets the Overshoot/Undershoot
Specifications...................................................................................... 25
2.5.6
Wired-OR Signals ................................................................................ 25
2.6
Voltage Regulator Connector Signals.................................................................... 27
2.7
System Bus Clock and Processor Clocking............................................................. 31
2.8
Recommended Connections for Unused Pins.......................................................... 33
Pinout Specifications ................................................................................................... 35
Mechanical Specifications............................................................................................. 65
4.1
Processor Package Dimensions ............................................................................ 65
4.1.1
Voltage Regulator (MVR) to Processor Package Interface........................... 71
4.2
Package Marking ............................................................................................... 72
4.2.1
Processor Top-Side Marking .................................................................. 72
4.2.2
Processor Bottom-Side Marking ............................................................. 73
Thermal Specifications ................................................................................................ 75
5.1
Thermal Features .............................................................................................. 75
5.1.1
Thermal Alert...................................................................................... 75
5.1.2
Enhanced Thermal Management ............................................................ 76
5.1.3
Power Trip .......................................................................................... 76
5.1.4
Thermal Trip ....................................................................................... 76
5.2
Case Temperature ............................................................................................. 76
System Management Feature Specifications ................................................................... 79
6.1
System Management Bus ................................................................................... 79
6.1.1
System Management Bus Interface ........................................................ 79
6.1.2
System Management Interface Signals ................................................... 79
6.1.3
SMBus Device Addressing ..................................................................... 81
6.2
Processor Information ROM ................................................................................ 82
6.3
Scratch EEPROM ............................................................................................... 85
2
3
4
5
6
Dual-Core Intel
®
Itanium
®
Processor 9000 and 9100 Series Datasheet
3
6.4
6.5
6.6
6.7
Processor Information ROM and Scratch EEPROM Supported SMBus
Transactions .....................................................................................................85
Thermal Sensing Device .....................................................................................86
Thermal Sensing Device Supported SMBus Transactions..........................................87
Thermal Sensing Device Registers........................................................................88
6.7.1
Thermal Reference Registers .................................................................88
6.7.2
Thermal Limit Registers ........................................................................89
6.7.3
Status Register ....................................................................................89
6.7.4
Configuration Register ..........................................................................89
6.7.5
Conversion Rate Register ......................................................................90
A
Signals Reference .......................................................................................................91
A.1
Alphabetical Signals Reference ............................................................................91
A.1.1 A[49:3]# (I/O).......................................................................................91
A.1.2 A20M# (I) .............................................................................................91
A.1.3 ADS# (I/O)............................................................................................91
A.1.4 AP[1:0]# (I/O).......................................................................................91
A.1.5 ASZ[1:0]# (I/O).....................................................................................91
A.1.6 ATTR[3:0]# (I/O) ...................................................................................92
A.1.7 BCLKp/BCLKn (I) ....................................................................................92
A.1.8 BE[7:0]# (I/O).......................................................................................92
A.1.9 BERR# (I/O) ..........................................................................................93
A.1.10 BINIT# (I/O)..........................................................................................94
A.1.11 BNR# (I/O)............................................................................................94
A.1.12 BPM[5:0]# (I/O) ....................................................................................94
A.1.13 BPRI# (I) ..............................................................................................94
A.1.14 BR[0]# (I/O) and BR[3:1]# (I).................................................................94
A.1.15 BREQ[3:0]# (I/O)...................................................................................95
A.1.16 CCL# (I/O) ............................................................................................96
A.1.17 CPUPRES# (O) .......................................................................................96
A.1.18 D[127:0]# (I/O).....................................................................................96
A.1.19 D/C# (I/O) ............................................................................................96
A.1.20 DBSY# (I/O) ..........................................................................................96
A.1.21 DBSY_C1# (O) .......................................................................................96
A.1.22 DBSY_C2# (O) .......................................................................................96
A.1.23 DEFER# (I) ............................................................................................96
A.1.24 DEN# (I/O)............................................................................................97
A.1.25 DEP[15:0]# (I/O) ...................................................................................97
A.1.26 DHIT# (I) ..............................................................................................97
A.1.27 DPS# (I/O) ............................................................................................98
A.1.28 DRDY# (I/O)..........................................................................................98
A.1.29 DRDY_C1# (O).......................................................................................98
A.1.30 DRDY_C2# (O).......................................................................................98
A.1.31 DSZ[1:0]# (I/O) ....................................................................................98
A.1.32 EXF[4:0]# (I/O) .....................................................................................98
A.1.33 FCL# (I/O) ............................................................................................99
A.1.34 FERR# (O).............................................................................................99
A.1.35 GSEQ# (I) .............................................................................................99
A.1.36 HIT# (I/O) and HITM# (I/O) ....................................................................99
A.1.37 ID[9:0]# (I) ..........................................................................................99
A.1.38 IDS# (I)................................................................................................99
A.1.39 IGNNE# (I)............................................................................................99
A.1.40 INIT# (I) ...............................................................................................99
A.1.41 INT (I) ................................................................................................ 100
A.1.42 IP[1:0]# (I) ......................................................................................... 100
A.1.43 LEN[2:0]# (I/O) ................................................................................... 100
A.1.44 LINT[1:0] (I) ....................................................................................... 100
4
Dual-Core Intel
®
Itanium
®
Processor 9000 and 9100 Series Datasheet
A.2
A.1.45 LOCK# (I/O)........................................................................................ 100
A.1.46 NMI (I) ............................................................................................... 101
A.1.47 OWN# (I/O) ........................................................................................ 101
A.1.48 PMI# (I) ............................................................................................. 101
A.1.49 PWRGOOD (I) ...................................................................................... 101
A.1.50 REQ[5:0]# (I/O) .................................................................................. 101
A.1.51 RESET# (I) ......................................................................................... 102
A.1.52 RP# (I/O) ........................................................................................... 102
A.1.53 RS[2:0]# (I) ....................................................................................... 103
A.1.54 RSP# (I) ............................................................................................. 103
A.1.55 SBSY# (I/O)........................................................................................ 103
A.1.56 SBSY_C1# (O)..................................................................................... 103
A.1.57 SBSY_C2# (O)..................................................................................... 103
A.1.58 SPLCK# (I/O) ...................................................................................... 103
A.1.59 STBn[7:0]# and STBp[7:0]# (I/O) ......................................................... 103
A.1.60 TCK (I) ............................................................................................... 104
A.1.61 TDI (I)................................................................................................ 104
A.1.62 TDO (O).............................................................................................. 104
A.1.63 THRMTRIP# (O) ................................................................................... 104
A.1.64 THRMALERT# (O)................................................................................. 104
A.1.65 TMS (I) ............................................................................................... 104
A.1.66 TND# (I/O) ......................................................................................... 104
A.1.67 TRDY# (I) ........................................................................................... 105
A.1.68 TRST# (I) ........................................................................................... 105
A.1.69 WSNP# (I/O)....................................................................................... 105
Signal Summaries ........................................................................................... 105
Figures
2-1
2-2
2-3
2-4
2-5
2-6
3-1
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
5-1
5-2
6-1
Generic Clock Waveform .................................................................................... 21
SMSC Clock Waveform ....................................................................................... 22
System Bus Signal Waveform Exhibiting Overshoot/Undershoot............................... 23
Processors Power Tab Physical Layout .................................................................. 28
System Bus Reset and Configuration Timings for Cold Reset.................................... 31
System Bus Reset and Configuration Timings for Warm Reset ................................. 32
Dual-Core Intel
®
Itanium
®
Processor 9000 and 9100 Series Pinout.......................... 35
Processor Package............................................................................................. 66
Package Height and Pin Dimensions ..................................................................... 67
Processor Package Mechanical Interface Dimensions .............................................. 69
Processor Package Top-Side Components Height Dimensions .................................. 70
Processor Package Bottom-Side Components Height Dimensions ............................. 70
Processor to MVR Interface Loads ........................................................................ 71
Processor Top-Side Marking on IHS ..................................................................... 73
Processor Bottom-Side Marking Placement on Interposer ........................................ 74
Dual-Core Intel
®
Itanium
®
Processor 9000 and 9100 Series Thermal
Features .......................................................................................................... 75
Itanium
®
Processor Package Thermocouple Location .............................................. 77
Logical Schematic of SMBus Circuitry ................................................................... 80
Dual-Core Intel
®
Itanium
®
Processor 9000 and 9100 Series Datasheet
5
