NS32CG16-10 NS32CG16-15 High-Performance Printer Display Processor
PRELIMINARY
November 1995
NS32CG16-10 NS32CG16-15
High-Performance Printer Display Processor
General Description
The NS32CG16 is a 32-bit microprocessor in the Series
32000 EP
TM
family that provides special features for graph-
ics applications It is specifically designed to support page
oriented printing technologies such as Laser LCS LED
Ion-Deposition and InkJet
The NS32CG16 provides a 16 Mbyte linear address space
and a 16-bit external data bus It also has a 32-bit ALU an
eight-byte prefetch queue and a slave processor interface
The capabilities of the NS32CG16 can be expanded by us-
ing an external floating point unit which interfaces to the
NS32CG16 as a slave processor This combination pro-
vides optimal support for outline character fonts
The NS32CG16’s highly efficient architecture in addition to
the built-in capabilities for supporting BITBLT (BIT-aligned
BLock Transfer) operations and other special graphics func-
tions make the device the ideal choice to handle a variety
of page description languages such as Postscript
TM
and
PCL
TM
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Software compatible with the Series 32000 EP
processors
32-bit architecture and implementation
Special support for graphics applications
18 graphics instructions
Binary compression expansion capability for font
storage using RLL encoding
Pattern magnification
Interface to an external BITBLT processing units for
fast color BITBLT operations
On-chip clock generator
Floating-point support via the NS32081 or NS32181
Optimal interface to large memory arrays via the
NS32CG821 and the DP84xx family of DRAM control-
lers
Power save mode
High-speed CMOS technology
68-pin PLCC package
Block Diagram
TL EE 9424 – 1
Series 32000 is a registered trademark of National Semiconductor Corporation
EP
TM
Embedded System Processors
TM
are trademarks of National Semiconductor Corporation
Postscript
TM
is a trademark of Adobe Systems Inc
PCL
TM
is a trademark of Hewlett Packard
C
1995 National Semiconductor Corporation
TL EE 9424
RRD-B30M115 Printed in U S A
Table of Contents
1 0 PRODUCT INTRODUCTION
1 1 NS32CG16 Special Features
2 0 ARCHITECTURAL DESCRIPTION
2 1 Register Set
2 1 1 General Purpose Registers
2 1 2 Address Registers
2 1 3 Processor Status Register
2 1 4 Configuration Register
2 2 Memory Organization
2 3 Modular Software Support
2 4 Instruction Set
2 4 1 General Instruction Format
2 4 2 Addressing Modes
2 4 3 Instruction Set Summary
2 4 Graphic Support
2 5 1 Frame Buffer Addressing
2 5 2 BITBLT Fundamentals
2 5 2 1 Frame Buffer Architecture
2 5 2 2 BIT Alignment
2 5 2 3 Block Boundaries and Destination
Masks
2 5 2 4 BITBLT Directions
2 5 2 5 BITBLT Variations
2 5 3 Graphics Support Instructions
2 5 3 1 BITBLT (BIT-aligned BLock Transfer)
2 5 3 2 Pattern Fill
2 5 3 3 Data Compression Expansion and
Magnify
2 5 3 3 1 Magnifying Compressed Data
3 0 FUNCTIONAL DESCRIPTION
3 1 Instruction Execution
3 1 1 Operating States
3 1 2 Instruction Endings
3 1 2 1 Completed Instructions
3 1 2 2 Suspended Instructions
3 1 2 3 Terminated Instructions
3 1 2 3 Partially Completed Instructions
3 1 3 Slave Processor Instructions
3 1 3 1 Slave Processor Protocol
3 1 3 2 Floating-Point Instructions
3 2 Exception Processing
3 2 1 Exception Acknowledge Sequence
3 2 2 Returning from an Exception Service Procedure
3 2 3 Maskable Interrupts
3 2 3 1 Non-Vectored Mode
3 2 3 2 Vectored Mode Non-Cascaded Case
3 2 3 3 Vectored Mode Cascaded Case
3 0 FUNCTIONAL DESCRIPTION
(Continued)
3 2 4 Non-Maskable Interrupt
3 2 5 Traps
3 2 6 Priority among Exceptions
3 2 7 Exception Acknowledge Sequences Detailed
Flow
3 2 7 1 Maskable Non-Maskable Interrupt
Sequence
3 2 7 2 SLAVE ILL SVC DVZ FLG BPT UND
Trap Sequence
3 2 7 3 Trace Trap Sequence
3 3 Debugging Support
3 3 1 Instruction Tracing
3 4 System Interface
3 4 1 Power and Grounding
3 4 2 Clocking
3 4 3 Power Save Mode
3 4 4 Resetting
3 4 5 Bus Cycles
3 4 5 1 Bus Status
3 4 5 2 Basic Read and Write Cycles
3 4 5 3 Cycle Extension
3 4 5 4 Instruction Fetch Cycles
3 4 5 5 Interrupt Control Cycles
3 4 5 6 Slave Processor Bus Cycles
3 4 5 7 Data Access Sequences
3 4 5 8 Bus Access Control
3 4 5 9 Instruction Status
4 0 DEVICE SPECIFICATIONS
4 1 NS32CG16 Pin Descriptions
4 1 1 Supplies
4 1 2 Input Signals
4 1 3 Output Signals
4 1 4 Input-Output Signals
4 2 Absolute Maximum Ratings
4 3 Electrical Characteristics
4 4 Test Loading Characteristics
4 5 Switching Characteristics
4 5 1 Definitions
4 5 2 Timing Tables
4 5 2 1 Output Signals Internal Propagation
Delays
4 5 2 2 Input Signal Requirements
4 5 3 Timing Diagrams
2
Table of Contents
(Continued)
Appendix A INSTRUCTION FORMATS
Appendix B INSTRUCTION EXECUTION TIMES
B 1 Basic and Floating-Point Instructions
B 1 1 Equations
B 1 2 Notes on Table Use
B 1 3 Calculation of the Execution Time
TEX for Basic Instructions
B 1 4 Calculation of the Execution Time
TEX for Floating-Point Instructions
B 2 Special Graphics Instructions
B 2 1 Execution Time Calculation for
Special Graphics Instructions
3
List of Illustrations
CPU Block Diagram
NS32FX16 Internal Registers
Processor Status Register (PSR)
Configuration Register (CFG)
NS32CG16 Run-Time Environment
General Instruction Format
Index Byte Format
Displacement Encodings
Correspondence between Linear and Cartesian Addressing
32-Pixel by 32-Scan Line Frame Buffer
Overlapping BITBLT Blocks
B B Instructions Format
BITWT Instruction Format
EXTBLT Instruction Format
MOVMPi Instruction Format
TBITS Instruction Format
SBITS Instruction Format
SBITPS Instruction Format
Bus Activity for a Simple BITBLT Operation
Operating States
Slave Processor Protocol
Slave Processor Status Word
Interrupt Dispatch Table
Exception Acknowledge Sequence
Return from Trap (RETTn) Instruction Flow
Return from Interrupt (RETI) Instruction Flow
Interrupt Control Unit Connections (16 Levels)
Cascaded Interrupt Control Unit Connections
Exception Processing Flowchart
Service Sequence
Power and Ground Connections
Crystal Interconnections 20 MHz 30 MHz
Crystal Interconnections 30 MHz
Recommended Reset Connections
Power-On Reset Requirements
General Reset Timings
Bus Connections
Read Cycle Timing
Write Cycle Timing
1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13a
3-13b
3-14
3-15
3-16
3-17
3-18
3-19
4
List of Illustrations
(Continued)
Cycle Extension of a Read Cycle
Slave Processor Read Cycle
Slave Processor Write Cycle
NS32FX16 and FPU Interconnections
Memory Interface
HOLD Timing Bus Initially Idle
HOLD Timing Bus Initially Not Idle
Connection Diagram
Test Loading Configuration
Output Signals Specification Standard
Input Signals Specification Standard
Read Cycle
Write Cycle
HOLD Acknowledge Timing (Bus Initially Not Idle)
HOLD Timing (Bus Initially Idle)
External DMA Controller Bus Cycle
Slave Processor Write Timing
Slave Processor Read Timing
SPC Timing
PFS Signal Timing
ILO Signal Timing
Clock Waveforms
INT Signal Timing
NITI Signal Timing
Power-On Reset
Non-Power-On Reset
3-20
3-21
3-22
3-23
3-24
3-25
3-26
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
List of Tables
NS32FX16 Addressing Modes
NS32FX16 Instruction Set Summary
‘op’ and ‘i’ Field Encodings
Floating-Point Instruction Protocols
Summary of Exception Processing
External Oscillator Specifications
Interrupt Sequences
Bus Cycle Categories
Data Access Sequences
Basic Instructions
Floating-Point Instructions CPU Portion
Average Instruction Execution Times with No Wait-States
Average Instruction Execution Times with Wait-States
2-1
2-2
2-3
3-1
3-2
3-3
3-4
3-5
3-6
B-1
B-2
B-3
B-4
5
