NT256D72S89AKGU
256MB : 32M x 72
Low Profile Registered DDR SDRAM DIMM
184pin Low Profile Registered DDR SDRAM MODULE
Based on 32Mx8 DDR SDRAM
Features
• 184-Pin 1U Registered 8-Byte Dual In-Line Memory Module
• 32Mx72 Double Data Rate (DDR) SDRAM DIMM
• Performance:
PC1600
Speed Sort
DIMM
CAS
Latency
f
CK
Clock Frequency
t
CK
Clock Cycle
f
DQ
DQ Burst Frequency
*
one-half clock post-amble
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
PC2100
-75B
3.5
133
7.5
266
-7K
3
133
7.5
266
MHz
ns
MHz
Unit
-8B
3
100
10
200
- Device
CAS
Latency: 2, 2.5
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 13/10/1 Addressing (row/column/bank)
• 7.8 µs Max. Average Periodic Refresh Interval
• Serial Presence Detect
• Gold contacts
• SDRAMs in 66-pin TSOP Type II Package
• Intended for 100 MHz and 133 MHz applications
• Inputs and outputs are SSTL-2 compatible
• V
DD
= 2.5Volt ± 0.2, V
DDQ
= 2.5Volt ± 0.2
• SDRAMs have 4 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
• Bi-directional data strobe with one clock cycle preamble and
*
One clock cycle added for registered DIMMs to account for input register.
Description
NT256D72S89AKGU is a Low Profile Registered 184-Pin 1U Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module
(DIMM), organized as a one-bank 32Mx72 high-speed memory array. The module uses nine 32Mx8 DDR SDRAMs in 400 mil TSOP II
packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs.
The use of these
common design files minimizes electrical variation between suppliers. All NANYA 184 DDR SDRAM DIMMs provide a high-performance,
flexible 8-byte interface in a 5.25” long space-saving footprint.
The DIMM is intended for use in applications operating up to 133 MHz clock speeds and achieves high-speed data transfer rates of up to
266 MHz. Prior to any access operation, the device
CAS
latency and burst type/ length/operation type must be programmed into the
DIMM by address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle. Clock enable CKE0 controls all devices
on the DIMM.
The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of
serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
Ordering Information
Part Number
NT256D72S89AKGU-7K
Speed
143MHz (7ns @ CL = 2.5)
133MHz (7.5ns @ CL= 2)
133MHz (7.5ns @ CL= 2.5)
100MHz (10ns @ CL = 2)
125MHz (8ns @ CL = 2.5)
100MHz (10ns @ CL = 2)
DDR266A
PC2100
Organization
Leads
Power
NT256D72S89AKGU-75B
DDR266B
PC2100
32Mx72
Gold
2.5V
NT256D72S89AKGU-8B
DDR200
PC1600
REV 0.2 (Preliminary)
09/2002
1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT256D72S89AKGU
256MB : 32M x 72
Low Profile Registered DDR SDRAM DIMM
Pin Description
CK0,
CK0
CKE0
RAS
CAS
WE
S0
A0-A9, A11, A12
A10/AP
BA0, BA1
RESET
V
REF
V
DDID
Differential Clock Inputs
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address Inputs
Address Input/Autoprecharge
SDRAM Bank Address Inputs
Reset pin
Ref. Voltage for SSTL_2 inputs
V
DD
Identification flag.
DQ0-DQ63
CB0-CB7
DQS0-DQS17
V
DD
V
DDQ
V
SS
NC
SCL
SDA
SA0-2
V
DDSPD
Data input/output
Check Bit Data Input/Output
Bidirectional data strobes
Power (2.5V)
Supply voltage for DQs(2.5V)
Ground
No Connect
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
Serial Presence Detect Address Inputs
Serial EEPROM positive power supply(2.5V)
Pinout
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Front
V
REF
DQ0
V
SS
DQ1
DQS0
DQ2
V
DD
DQ3
NC
RESET
V
SS
DQ8
DQ9
DQS1
V
DDQ
NC
NC
V
SS
DQ10
DQ11
CKE0
V
DDQ
DQ16
DQ17
DQS2
V
SS
A9
DQ18
A7
V
DDQ
DQ19
53
54
55
56
57
58
59
60
61
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Front
A5
DQ24
V
SS
DQ25
DQS3
A4
V
DD
DQ26
DQ27
A2
V
SS
A1
CB0
CB1
V
DD
DQS8
A0
CB2
V
SS
CB3
BA1
KEY
DQ32
V
DDQ
DQ33
DQS4
DQ34
V
SS
BA0
DQ35
DQ40
Pin
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Front
V
DDQ
WE
DQ41
CAS
V
SS
DQS5
DQ42
DQ43
V
DD
NC
DQ48
DQ49
V
SS
NC
NC
V
DDQ
DQS6
DQ50
DQ51
V
SS
V
DDID
DQ56
DQ57
V
DD
DQS7
DQ58
DQ59
V
SS
NC
SDA
SCL
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
Back
V
SS
DQ4
DQ5
V
DDQ
DQS9
DQ6
DQ7
V
SS
NC
NC
NC
V
DDQ
DQ12
DQ13
DQS10
V
DD
DQ14
DQ15
NC
V
DDQ
NC
DQ20
A12
V
SS
DQ21
A11
DQS11
V
DD
DQ22
A8
DQ23
145
146
147
148
149
150
151
152
153
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Back
V
SS
A6
DQ28
DQ29
V
DDQ
DQS12
A3
DQ30
V
SS
DQ31
CB4
CB5
V
DDQ
CK0
CK0
V
SS
DQS17
A10
CB6
V
DDQ
CB7
KEY
V
SS
DQ36
DQ37
V
DD
DQS13
DQ38
DQ39
V
SS
DQ44
Pin
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Back
RAS
DQ45
V
DDQ
S0
NC
DQS14
V
SS
DQ46
DQ47
NC
V
DDQ
DQ52
DQ53
NC
V
DD
DQS15
DQ54
DQ55
V
DDQ
NC
DQ60
DQ61
V
SS
DQS16
DQ62
DQ63
V
DDQ
SA0
SA1
SA2
V
DDSPD
REV 0.2 (Preliminary)
09/2002
2
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT256D72S89AKGU
256MB : 32M x 72
Low Profile Registered DDR SDRAM DIMM
Input/Output Functional Description
Symbol
CK0
Type
(SSTL)
Polarity
Positive
Edge
Function
The positive line of the differential pair of system clock inputs which drives the input to
the on-DIMM PLL. All the DDR SDRAM address and control inputs are sampled on the
rising edge of their associated clocks.
the on-DIMM PLL.
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh
mode.
Enables the associated SDRAM command decoder when low and disables the
S0
(SSTL)
Active
Low
Active
Low
command
decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue.
RAS
,
CAS
,
WE
V
REF
V
DDQ
BA0, BA1
(SSTL)
Supply
Supply
(SSTL)
-
When sampled at the positive rising edge of the clock,
RAS
,
CAS
,
WE
define the
operation to be executed by the SDRAM.
Reference voltage for SSTL-2 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9, A11 defines the column address
(CA0-CA10) when sampled at the rising clock edge. In addition to the column address,
A0 - A9
A10/AP
A11, A12
AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write
(SSTL)
-
cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be
precharged. If AP is low, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to
pre-charge.
DQ0 - DQ63,
DQ0 – DQ63
CB0 – CB7
V
DD,
V
SS
DQS0 – DQS17
(SSTL)
(SSTL)
Supply
-
Active
High
Data and Check Bit input/output pins operate in the same manner as on conventional
DRAMs.
Data and Check Bit Input/Output pins. Check bits are only applicable on the x72 DIMM
configurations.
Power and ground for the DDR SDRAM input buffers and core logic
CK0
(SSTL)
(SSTL)
Negative The negative line of the differential pair of system clock inputs which drives the input to
Edge
Active
High
CKE0
RESET
SA0 – SA2
SDA
SCL
V
DDSPD
Negative
and
(SSTL)
Data strobe for input and output data
Positive
Edge
Active
(LVC-MOS)
Low
Address inputs. Connected to either V
DD
or V
SS
on the system board to configure the
-
Serial Presence Detect EEPROM address.
-
-
Supply
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V
DD
to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V
DD
to act as a pullup.
Serial EEPROM positive power supply.
REV 0.2 (Preliminary)
09/2002
3
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT256D72S89AKGU
256MB : 32M x 72
Low Profile Registered DDR SDRAM DIMM
Functional Block Diagram
(1 Bank, 32Mx8 DDR SDRAMs)
RS0
DQS0
DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS8
DQS17
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DQS16
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DQS15
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DQS14
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DQS4
DQS13
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
D0
D4
D1
D5
D2
D6
D3
D7
D8
S0
BA0-BA1
A0-A12
RAS
CAS
CKE0
WE
PCK
PCK
Notes :
R
E
G
I
S
T
E
R
RS0
RBA0-RBA1
RA0-RA12
RRAS
RCAS
RCKE0
RWE
RESET
CS
: SDRAMs D0-D8
BA0-BA1 : SDRAMs D0-D8
A0-A12 : SDRAMs D0-D8
RAS
: SDRAMs D0-D8
CAS
: SDRAMs D0-D8
CKE : SDRAMs D0-D8
WE
: SDRAMs D0-D8
V
DDSPD
V
DDQ
V
DD
V
REF
V
SS
V
DDID
Serial PD
D0-D8
D0-D8
D0-D8
D0-D8
Strap : see Note 4
Serial PD
SCL
WP A0
SA0
A1
SA1
A2
SA2
SDA
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/CS relationships are maintained as shown.
3. DQ/DQS resistors are 22 Ohms.
4. V
DDID
strap connections (for memory device V
DD
,V
DDQ
):
STRAP OUT (OPEN): V
DD
= V
DDQ
STRAP IN (V
SS
): V
DD
is not equal to V
DDQ
5. Address and control resistors are 22 Ohms.
CK0,
CK0
--------- PLL*
* Wire per Clock Loading Table/Wiring Diagrams
REV 0.2 (Preliminary)
09/2002
4
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT256D72S89AKGU
256MB : 32M x 72
Low Profile Registered DDR SDRAM DIMM
Serial Presence Detect --
Part 1 of 2
32Mx72 1 BANK REGISTERED DDR SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD
SPD Entry Value
Byte
Description
Number of Serial PD Bytes Written during
Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Bank
Data Width of Assembly
Data Width of Assembly (cont’)
Voltage Interface Level of this Assembly
DDR SDRAM Device Cycle Time at CL=2.5
DDR SDRAM Device Access Time from
Clock at CL=2.5
DIMM Configuration Type
Refresh Rate/Type
Primary DDR SDRAM Width
Error Checking DDR SDRAM Device Width
DDR SDRAM Device Attr: Min CLk Delay,
Random Col Access
DDR SDRAM Device Attributes:
Burst Length Supported
DDR SDRAM Device Attributes: Number of
Device Banks
DDR SDRAM Device Attributes: CAS
Latencies Supported
DDR SDRAM Device Attributes: CS Latency
DDR SDRAM Device Attributes: WE Latency
DDR SDRAM Device Attributes:
DDR SDRAM Device Attributes: General
Minimum Clock Cycle at CL=2
Maximum Data Access Time from Clock at
CL=2
Minimum Clock Cycle Time at CL=1
Maximum Data Access Time from Clock at
CL=1
Minimum Row Precharge Time (t
RP
)
Minimum Row Active to Row Active delay
(t
RRD
)
Minimum RAS to CAS delay (t
RCD
)
Minimum RAS Pulse Width (t
RAS
)
Module Bank Density
Address and Command Setup Time Before
Clock
Address and Command Hold Time After
Clock
Data Input Setup Time Before Clock
Data Input Hold Time After Clock
Reserved
SPD Revision
Checksum Data
Initial
0.9ns
0.9ns
0.5ns
0.5ns
20ns
15ns
20ns
45ns
2/2.5
7ns
0.75ns
DDR266A DDR266B
-7K
0
1
2
3
4
5
6.
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
-75B
128
256
SDRAM DDR
13
11
1
X72
X72
SSTL 2.5V
7.5ns
0.75ns
ECC
7.8us / SR
X8
X8
1 Clock
2, 4, 8
4
2/2.5
0
1
Differential Clock, PLL, REGISTER
+/-0.2V Voltage Tolerance
7.5ns
0.75ns
10ns
0.75ns
N/A
N/A
20ns
15ns
20ns
45ns
512MB
0.9ns
0.9ns
0.5ns
0.5ns
Undefined
Initial
Initial
00
A7
1.1ns
1.1ns
0.6ns
0.6ns
90
90
50
50
20ns
15ns
20ns
50ns
50
3C
50
2D
10ns
0.8ns
75
75
2/2.5
0C
8ns
0.8ns
70
75
DDR200
-8B
Serial PD Data Entry (Hexadecimal) Note
DDR266A DDR266B
-7K
-75B
80
08
07
0D
0A
01
48
00
04
75
75
02
82
08
08
01
0E
04
0C
01
02
26
00
A0
75
00
00
50
3C
50
2D
40
90
90
50
50
00
00
D7
00
5D
B0
B0
60
60
50
3C
50
32
A0
80
0C
80
80
DDR200
-8B
REV 0.2 (Preliminary)
09/2002
5
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
