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NT256S64V8HC0G

256MB : 32M x 64

Unbuffered SDRAM Module

32Mx64 bit Two Bank Unbuffered SDRAM Module

based on 16Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD

Features

168-Pin Unbuffered 8-Byte Dual In-Line Memory Module

Intended for PC133 applications

- Clock Frequency: 133MHz

- Clock Cycle: 7.5ns

- Clock Assess Time: 5.4ns

Inputs and outputs are LVTTL (3.3V) compatible

Single 3.3V

0.3V Power Supply

Single Pulsed RAS interface

SDRAMs have 4 internal banks

Module has 2 physical bank

Fully Synchronous to positive Clock Edge

Data Mask for Byte Read/Write control

Auto Refresh (CBR) and Self Refresh

Automatic and controlled Precharge commands

Programmable Operation:

- CAS Latency: 2, 3

- Burst Type: Sequential or Interleave

- Burst Length: 1, 2, 4, 8

- Operation: Burst Read and Write or Multiple Burst Read with

Single Write

Suspend Mode and Power Down Mode

4096 Refresh cycles distributed across 64ms

Gold contacts

SDRAMs in TSOP Type II Package

Serial Presence Detect with Write Protect

Description

NT256S64V8HC0G is unbuffered 168-pin Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which is organized as 32Mx64

high-speed memory arrays and is configured as two 16M x 64 physical bank. The DIMM uses sixteen 16Mx8 SDRAMs in 400mil TSOP II

pack-ages. The DIMM achieves high-speed data transfer rates of up to 133MHz by employing a prefetch / pipeline hybrid architecture that

supports the JEDEC 1N rule while allowing very low burst power.

All control, address, and data input/output circuits are synchronized with the positive edge of the externally supplied clock inputs.

All inputs are sampled at the positive edge of each externally supplied clock (CK0 - CK3). Internal operating modes are defined by combinations

RAS

CAS

, DQMB, and CKE0 – CKE1 signals. A command decoder initiates the necessary timings for each operation. A

14-bit address bus accepts address information in a row / column multiplexing arrangement.

Prior to any Access operation, the

CAS

latency, burst type, burst length, and Burst operation type must be programmed into the DIMM by

address inputs A0-A9 during the Mode Register Set cycle. The DIMM uses serial presence detects implemented via a serial EEPROM using

the two-pin IIC protocol. The first 128 bytes of serial PD data are used by the DIMM manufacturer. The last 128 bytes are available to the

customer.

Ordering Information

Speed

Part Number

MHz.

143MHz

NT256S64V8HC0G-7K

133MHz

NT256S64V8HC0G-75B

100MHz

125MHz

NT256S64V8HC0G-8B

100MHz

* CL = CAS Latency

32Mx64

Gold

3.3V

t RCD

t RP

Organization

Leads

Power

Preliminary

/ 2001

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256S64V8HC0G

256MB : 32M x 64

Unbuffered SDRAM Module

Pin Description

CK0 , CK1

CK2, CK3

CKE0 – CKE1

Clock Inputs

Clock Enable

Row Address Strobe

Column Address Strobe

Write Enable

Chip Selects

Address Inputs

Address Input/Autoprecharge

SDRAM Bank Address Inputs

DQ0-DQ63

CB0-CB7

DQMB0-DQMB7

SCL

SDA

SA0-2

Data input/output

Check Bit Data input/output

Data Mask

Power (3.3V)

Ground

No Connect

Serial Presence Detect Clock Input

Serial Presence Detect Data input/output

Serial Presence Detect Address Inputs

Serial Presence Detect Write Protect Input

RAS

CAS

A0-A9, A11

A10 / AP

BA0, BA1

Pinout

Front

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

CB0

CB1

100

101

102

103

104

105

106

107

108

109

110

111

112

Back

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

CB4

CB5

Front

DQMB1

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

Back

DQMB5

Front

DQ18

DQ19

DQ20

CKE1*

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

CK2

SDA

SCL

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

Back

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

CK3

SA0

SA1

SA2

A10/AP

BA1

CK0

RAS

BA0

A11

CK1

CKE0

DQMB2

DQMB3

CB2

CB3

DQ16

DQ17

DQMB6

DQMB7

CB6

CB7

DQ48

DQ49

DQMB0

CAS

DQMB4

Note: All pin assignments are consistent for all 8-byte unbuffered versions.

*CKE1 is terminated with a 10k ohm pullup resistor.

Preliminary

/ 2001

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256S64V8HC0G

256MB : 32M x 64

Unbuffered SDRAM Module

SDRAM DIMM Block Diagram

(2 Bank, 16Mx8 SDRAMs)

DQMB0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQMB1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQMB5

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D13

DQMB4

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D12

DQMB2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQMB3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D11

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D10

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQMB7

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D15

DQMB6

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D14

NOTE : Exact DQ wiring may differ from that shown above

CK0

CK1

CK2

CK3

A0 - A11

BA0

BA1

RAS

CAS

CKE0

CLK : SDRAMs D0 -D1, D4 - D5, 3.3pF Cap

CLK : SDRAMs D8 - D9,D12 - D13, 3.3pF Cap

CLK : SDRAMs D2 - D3,D6 -D7, 3.3pF Cap

CLK : SDRAMs D10 - D11, D14 -D15, 3.3pF Cap

A0 - A11 : SDRAMs D0 - D15

A13/BS0 : SDRAMs D0 - D15

A12/BS1 : SDRAMs D0 - D15

RAS : SDRAMs D0- D15

CAS : SDRAMs D0- D15

CKE : SDRAMs D0- D7

WE : SDRAMs D0- D15

CKE1

VDD

.33uF

VSS

0.1 uF

D0 - D15

Serial PD

SCL

47K

SA0

SA1

SA2

SDA

VDD

10K

CKE : SDRAMs D8- D15

D0 - D15

*All resistor values are 10 ohms except as shown.

Preliminary

/ 2001

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256S64V8HC0G

256MB : 32M x 64

Unbuffered SDRAM Module

Input/Output Functional Description

Symbol

CK0 , CK2

Type

Input

Signal

Pulse

Polarity

Positive

Edge

Active

CKE0

Input

Level

High

Active

their associated clock.

Activates the SDRAM CK0 and CK2 signals when high and deactivates them when low.

By deactivating the clocks, CKE0 low initiates the Power Down mode, Suspend mode, or

the Self-Refresh mode.

Enables the associated SDRAM command decoder when low and disables the

command decoder when high. When the command decoder is disabled, new commands

Low

Active

are ignored but previous operations continue.

When sampled at the positive rising edge of the clock,

RAS

CAS

define the

operation to be executed by the SDRAM.

Selects which SDRAM bank is to be active.

During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)

when sampled at the rising clock edge.

During a Read or Write command cycle, A0-A8 defines the column address (CA0-CA9)

A0 - A9

A10/AP

A11

Input

Level

when sampled at the rising clock edge. In addition to the column address, AP is used to

invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,

autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,

autoprecharge is disabled.

During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control

which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the

state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to

pre-charge.

DQ0 - DQ63,

CB0 - CB7

Input

Level

/Output

Data and Check Bit input/output pins operate in the same manner as on conventional

DRAMs.

The Data input/output mask places the DQ buffers in a high impedance state when

Active

DQMB0 -DQMB7

Input

Pulse

High

sampled high. In Read mode, DQM has a latency of two clock cycles and controls the

output buffers like an output enable. In Write mode, DQM has a latency of zero and

operates as a byte mask by allowing input data to be written if it is low but blocks the

Write operation if DQM is high.

SA0 – SA2

Input

SDA

/Output

Level

Address inputs. Connected to either V

or V

on the system board to configure the

Serial Presence Detect EEPROM address.

Serial Data. Bi-directional signal used to transfer data into and out of the Serial Presence

Detect EEPROM. Since the SDA signal is Open Drain/Open Collector at the EEPROM, a

pull-up resistor is required on the system board.

Serial Clock. Used to clock all Serial Presence Detect data into and out of the EEPROM.

SCL

Input

Pulse

Since the SCL signal is inactive in the “high” state, a pull-up resistor is recommended on

the system board.

Active

Input

Level

High

, V

Supply

Hardware Write Protect. When WP is active, writing to the EEPROM array is inhibited.

On the DIMM, this input is connected to the EEPROM Write Protect input and is also tied

to ground through a 47K ohm pull-down resistor.

Power and ground for the module.

Function

The system clock inputs. All of the SDRAM inputs are sampled on the rising edge of

Input

Pulse

RAS

CAS

BA0, BA1

Input

Pulse

Low

Input

Level

Preliminary

/ 2001

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT256S64V8HC0G

256MB : 32M x 64

Unbuffered SDRAM Module

Absolute Maximum Ratings

Symbol

OUT

STG

OUT

Parameter

Power Supply Voltage

Input Voltage

Output Voltage

Operating Temperature (ambient)

Storage Temperature

Power Dissipation

Short Circuit Output Current

Rating

-0.3 to +4.6

-0.3 to V

+0.3

-0.3 to V

+0.3

0 to +70

-55 to +125

6.9

Units

Notes

°C

1.1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.

This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Recommended DC Operating Conditions

=0 to 70

°C)

Rating

Symbol

Power Voltage

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

Input Leakage current

Parameter

Min.

3.0

2.0

-0.3

2.4

-10

Typ.

3.3

Max.

3.6

+ 0.3

0.8

0.4

1,2

1,3

Units

Notes

All voltages referenced to V

(max) = V

/ V

DDQ

+ 1.2V for pulse width

≤

5ns

(min) = V

/ V

SSQ

- 1.2V for pulse width

≤

5ns .

Capacitance

=25

°C

, f =1MHz, V

=3.3 ± 0.3V)

Symbol

IO1

IO2

Parameter

Input Capacitance (A0-A9, A10/AP, A11, BA0, BA1,

RAS

CAS

)

Input Capacitance (CKE0)

Input Capacitance (

)

Input Capacitance (CK0 - CK3)

Input Capacitance (DQMB0 - DQMB7)

Input Capacitance (SA0 - SA2, SCL, WP)

Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7)

Input/Output Capacitance (SDA)

Max.

104

Unit

DC Output Load Circuit

3.3 V

1200 ohms

Output

50 pF

870 ohms

VOH(DC) = 2.4V,IOH= -2mA

VOL(DC) = 0.4V,IOL= -2mA

Preliminary

/ 2001

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.