ASM5P2308A
3.3 V Zero-Delay Buffer
ASM5P2308A is a versatile, 3.3 V zero−delay buffer designed to
distribute high−speed clocks. It is available in a 16−pin package. The
part has an on−chip PLL which locks to an input clock presented on
the REF pin. The PLL feedback is required to be driven to FBK pin,
and can be obtained from one of the outputs. The input−to−output
propagation delay is guaranteed to be less than
±250
pS, and the
output−to−output skew is guaranteed to be less than 200 pS.
The ASM5P2308A has two banks of four outputs each, which can
be controlled by the select inputs as shown in the
Select Input
Decoding Table.
If all the output clocks are not required, Bank B can
be three−stated. The select input also allows the input clock to be
directly applied to the outputs for chip and system testing purposes.
Multiple ASM5P2308A devices can accept the same input clock
and distribute it. In this case the skew between the outputs of the two
devices is guaranteed to be less than 700 pS.
ASM5P2308A is available in five different configurations. Refer to
ASM5P2308A Configurations Table.
The ASM5P2308A−1 is the base
part, where the output frequencies equal the reference clock input. The
ASM5P2308A−1H is the high−drive version of the −1 and the rise and
fall times on this device are faster.
ASM5P2308A−2 allows the user to obtain 2x and 1x frequencies on
each output bank. The exact configuration and output frequencies
depends on which output drives the feedback pin. ASM5P2308A−3
allows the user to obtain 4x and 2x frequencies on the outputs.
ASM5P2308A−4 enables the user to obtain 2x clocks on all outputs.
The ASM5P2308A−5H is a high−drive version with REF/2 output
on both banks.
ASM5P2308A is an extremely versatile part, and can be used in a
variety of applications.
Features
Description
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SOIC−16
S SUFFIX
CASE 751BG
TSSOP−16
T SUFFIX
CASE 948AN
PIN CONFIGURATION
1
REF
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
(Top View)
FBK
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
•
Zero Input−output Propagation Delay, Adjustable by Capacitive Load
•
•
•
on FBK Input
Multiple Configurations –
Refer to
ASM5P2308A Configurations Table
Input Frequency Range: 10 MHz to 133 MHz
Multiple Low−skew Outputs
♦
Output−output Skew less than 200 pS
♦
Device−device Skew less than 700 pS
♦
Two Banks of Four Outputs Each,
Three−state by Two Select Inputs
Less than 200 pS Cycle−to−Cycle Jitter (−1, −1H, −2, −3, −4, −5H)
16−pin SOIC and TSSOP Packages
3.3 V Operation
Commercial and Industrial Temperature Range
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
•
•
•
•
•
© Semiconductor Components Industries, LLC, 2011
August, 2011
−
Rev. 3
1
Publication Order Number:
ASM5P2308A/D
ASM5P2308A
/2
REF
/2
FBK
PLL
MUX
CLKA1
Extra Divider (−5H)
Extra Divider (−3,
−4)
CLKA2
CLKA3
CLKA4
S2
Select
Input
Decoding
S1
/2
CLKB1
Extra Divider (−2,
−3)
CLKB2
CLKB3
Figure 1. Block Diagram
CLKB4
Table 1. SELECT INPUT DECODING FOR ASM5P2308A
S2
0
0
1
1
S1
0
1
0
1
Clock A1
−
A4
Three−state
Driven
Driven (Note 1)
Driven
Clock B1
−
B4
Three−state
Three−state
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shut−Down
Y
N
Y
N
1. Outputs are non−inverted on 2308A−2 and 2308A−3 in bypass mode, S2 = 1 and S1 = 0.
Table 2. ASM5P2308A CONFIGURATIONS
(This table is applicable when PLL is not Shut Down.)
Device
ASM5P2308A (−1,
−1H)
ASM5P2308A−2
ASM5P2308A−2
ASM5P2308A−3
ASM5P2308A−3
ASM5P2308A−4
ASM5P2308A−5H
Feedback From
Bank A or Bank B
Bank A
Bank B
Bank A
Bank B
Bank A or Bank B
Bank A or Bank B
Bank A Frequency
Reference
Reference
2 X Reference
2 X Reference
4 X Reference
2 X Reference
Reference /2
Bank B Frequency
Reference
Reference /2
Reference
Reference or Reference (Note 2)
2 X Reference
2 X Reference
Reference /2
2. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the ASM5P2308A−2.
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2
ASM5P2308A
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero Delay between input and output.
1500
REF−Input to CLKA / CLKB Delay (pS)
1000
500
0
−30 −25
−500
−20
−15
−10
−5
0
5
10
15
20
25
30
−1000
−1500
Figure 2. Output Load Difference: FBK Load
−
CLKA/CLKB Load (pF)
To close the feedback loop of the ASM5P2308A, the FBK
can be driven from any of the eight available clock outputs.
The output driving the FBK pin will be driving a total load
of 7 pF plus any additional load that it drives. The relative
loading of this output (with respect to the remaining outputs)
can adjust the input−output delay. This is shown in the above
graph.
Table 3. PIN DESCRIPTION FOR ASM5P2308A
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
REF (Note 3)
CLKA1 (Note 4)
CLKA2 (Note 4)
V
DD
GND
CLKB1 (Note 4)
CLKB2 (Note 4)
S2 (Note 5)
S1 (Note 5)
CLKB3 (Note 4)
CLKB4 (Note 4)
GND
V
DD
CLKA3 (Note 4)
CLKA4 (Note 4)
FBK
For applications requiring zero input−output delay, all
outputs including the one providing feedback should be
equally loaded. If input−output delay adjustments are
required, use the above graph to calculate loading
differences between the feedback output and remaining
outputs. For zero output−output skew, be sure to load outputs
equally.
Description
Input reference clock frequency, 5 V tolerant input
Buffered clock output, bank A
Buffered clock output, bank A
3.3 V supply
Ground
Buffered clock output, bank B
Buffered clock output, bank B
Select input, bit 2
Select input, bit 1
Buffered clock output, bank B
Buffered clock output, bank B
Ground
3.3 V supply
Buffered clock output, bank A
Buffered clock output, bank A
PLL feedback input
3. Weak pull−down.
4. Weak pull−down on all outputs.
5. Weak pull−up on these inputs.
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ASM5P2308A
Table 4. ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
DC Input Voltage (REF)
Storage Temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (As per JEDEC STD22− A114−B)
Min
−0.5
−0.5
−0.5
−65
Max
+4.6
V
DD
+ 0.5
7
+150
260
150
2000
Unit
V
V
V
°C
°C
°C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 5. OPERATING CONDITIONS
Parameter
V
DD
T
A
Supply Voltage
Operating Temperature
(Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance (Note 6)
Commercial temperature
Industrial temperature
Description
Min
3.0
0
−40
Max
3.6
70
85
30
15
7
pF
pF
pF
Unit
V
°C
C
L
C
L
C
IN
6. Applies to both Ref Clock and FBK.
Table 6. ELECTRICAL CHARACTERISTICS
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Voltage
(Note 7)
Output HIGH Voltage
(Note 7)
Supply Current
(Note 8)
V
IN
= 0 V
V
IN
= V
DD
I
OL
= 8 mA (−1,
−2, −3, −4)
I
OL
= 12 mA (−1H,
−5H)
I
OH
=
−8
mA (−1,
−2, −3, −4)
I
OH
=
−12
mA (−1H,
−5H)
Unloaded outputs at 100 MHz,
Select inputs at V
DD
or GND
(−1,
−1H, −2,−3,−4)
Unloaded outputs; 100 MHz
REF, Select inputs at V
DD
or
GND (−5H)
Unloaded outputs at 66 MHz
Commercial temp.
Industrial temp.
Commercial temp.
Industrial temp.
Commercial temp.
Industrial temp.
Unloaded outputs at 33 MHz
Commercial temp.
Industrial temp.
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
8. Supply Currents are measured for PLL−Driven Mode (S2 = 1, S1 = 1).
2.4
40
45
30
35
32
34
18
20
2.2
50
100
0.4
Test Conditions
Min
Max
0.8
Unit
V
V
½-tA
½-tA
V
V
mA
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ASM5P2308A
Table 7. SWITCHING CHARACTERISTICS
(For all measurements use Test Circuit #1.) (Note 9)
Parameter
Output Frequency
(Refer to
ASM5P2308A
Configurations Table)
30 pF load
Test Conditions
(
−1, −1H)
(−2)
(−3)
(−4)
(−5H)
15 pF load
(
−1, −1H)
(−2)
(−3)
(−4)
Duty Cycle (Note 10)
(−1,
−2, −3, −4, −1H, −5H)
Duty Cycle (Note 10)
(−1,
−2, −3, −4, −1H, −5H)
Output Rise Time (Note 10)
(−1,
−2, −3, −4)
Output Rise Time (Note 10)
(−1,
−2, −3, −4)
Output Rise Time (Note 10)
(−1H,
−5H)
Output Fall Time (Note 10)
(−1,
−2, −3, −4)
Output Fall Time (Note 10)
(−1,
−2, −3, −4)
Output Fall Time (Note 10)
(−1H,
−5H)
Measured at 1.4 V, F
OUT
≤ 66.66 MHz, 30 pF load
Measured at 1.4 V, F
OUT
≤ 50 MHz, 15 pF load
Measured between 0.8 V
and 2.0 V, 30 pF load
Measured between 0.8 V
and 2.0 V, 15 pF load
Measured between 0.8 V
and 2.0 V, 30 pF load
Measured between 2.0 V
and 0.8 V, 30 pF load
Measured between 2.0 V
and 0.8 V, 15 pF load
Measured between 2.0 V
and 0.8 V, 30 pF load
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
Commercial temp.
Industrial temp.
Commercial temp.,
Industrial temp.
1.25
Commercial temp.
Industrial temp.
Commercial temp.,
Industrial temp.
1.5
Min
10
12
15
20
5
10
12
15
20
40
45
50
50
Typ
Max
100
100
100
100
66.67
133
133
133
133
60
55
2.2
2.5
1.5
2
2.2
2.5
1.5
1.5
200
200
200
400
0
0
±250
700
200
200
125
400
nS
nS
pS
pS
pS
pS
pS
nS
nS
nS
%
%
nS
MHz
Unit
MHz
Output−to−output skew on same bank (Note 10)
(−1,
−2, −3, −4)
Output−to−output skew (Note 10) (−1H,
−5H)
Output bank A
−to−
output Bank B skew (Note 10)
(−1,
−4, −5H)
Output bank A
−to−
output
Bank B skew (Note 10) (−2,
−3)
Delay, REF Rising Edge to FBK
Rising Edge (Notes 10, 11)
Device−to−Device Skew
(Note 10)
Cycle−to−Cycle Jitter (Note 10)
(−1,
−1H, −4, −5H)
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on the FBK pins of the device
Measured at 66.67 MHz, loaded outputs, 15 pF load
Measured at 66.67 MHz, loaded outputs, 30 pF load
Measured at 133.3 MHz, loaded outputs, 15 pF load
(Note 12)
Cycle−to−Cycle Jitter (Note 10)
(−2,
−3)
PLL Lock Time (Note 10)
Measured at 66.67 MHz, loaded outputs, 15 pF load
Measured at 66.67 MHz, loaded outputs, 30 pF load
Stable power supply, valid clock presented on REF and
FBK pins
1.0
mS
9. All parameters are specified at Commercial and Industrial temperature unless stated otherwise.
10. Parameter is guaranteed by design and characterization. Not 100% tested in production.
11. Refer to Test Circuit #2 *Not applicable for (−1,
−2, −1H, −2H).
12. Not applicable for
−5H.
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