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PCA9510A

Hot swappable I

C-bus and SMBus bus buffer

Rev. 01 — 8 September 2005

Product data sheet

1. General description

The PCA9510A is a hot swappable I

C-bus and SMBus buffer that allows I/O card

insertion into a live backplane without corrupting the data and clock buses. Control

circuitry prevents the backplane from being connected to the card until a stop command or

bus idle occurs on the backplane without bus contention on the card. When the

connection is made, the PCA9510A provides bidirectional buffering, keeping the

backplane and card capacitances isolated.

The PCA9510A has no rise time accelerator circuitry to prevent interference when there

are multiple devices in the same system. The PCA9510A incorporates a digital ENABLE

input pin, which enables the device when asserted HIGH and forces the device into a Low

current mode when asserted LOW, and an open-drain READY output pin, which indicates

that the backplane and card sides are connected together (HIGH) or not (LOW).

During insertion, the PCA9510A SDAIN and SCLIN pins (inputs only) are precharged to

1 V to minimize the current required to charge the parasitic capacitance of the chip.

Remark:

The dynamic offset design of the PCA9510A/11A/12A/13A/14A I/O drivers allow

them to be connected to another PCA9510A/11A/12A/13A/14A device in series or in

parallel and to the A side of the PCA9517. The PCA9510A/11A/12A/13A/14A

cannot

connect to the static offset I/Os used on the PCA9515/15A/16/16A/18 or PCA9517 B side

or P82B96 Sx/y side.

2. Features

Bidirectional buffer for SDA and SCL lines increases fanout and prevents SDA and

SCL corruption during live board insertion and removal from multi-point backplane

systems

Compatible with I

C-bus Standard mode, I

C-bus Fast mode, and SMBus standards

Active HIGH ENABLE input

Active HIGH READY open-drain output

High-impedance SDAn and SCLn pins for V

= 0 V

1 V precharge on SDAIN and SCLIN inputs

Supports clock stretching and multiple master arbitration and synchronization

Operating power supply voltage range: 2.7 V to 5.5 V

I/Os are not 5.5 V tolerant

0 Hz to 400 kHz clock frequency

ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

Packages offered: SO8, TSSOP8 (MSOP8)

Philips Semiconductors

PCA9510A

Hot swappable I

C-bus and SMBus bus buffer

3. Applications

cPCI, VME, AdvancedTCA cards and other multi-point backplane cards that are

required to be inserted or removed from an operating system

4. Feature selection

Table 1:

Feature

Idle detect

High-impedance SDA, SCL pins for V

= 0 V

Rise time accelerator circuitry on SDAn and SCLn pins

Rise time accelerator circuitry hardware disable pin for

lightly loaded systems

Rise time accelerator threshold 0.8 V versus 0.6 V

improves noise margin

Ready open-drain output

Feature selection chart

PCA9510A PCA9511A PCA9512A PCA9513A PCA9514A

yes

Two V

pins to support 5 V to 3.3 V level translation with -

improved noise margins

1 V precharge on all SDAn and SCLn pins

µA

current source on SCLIN and SDAIN for PICMG

applications

in only

5. Ordering information

Table 2:

Ordering information

amb

−

C to +85

Type number

PCA9510AD

PCA9510ADP

[1]

Topside

mark

PA9510A

9510A

Package

Name

SO8

TSSOP8

[1]

Description

plastic small outline package; 8 leads; body width 3.9 mm

Version

SOT96-1

plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1

Also known as MSOP8.

Standard packing quantities and other packaging data are available at

www.standardics.philips.com/packaging/.

PCA9510A_1

Product data sheet

Rev. 01 — 8 September 2005

2 of 23

Philips Semiconductors

PCA9510A

Hot swappable I

C-bus and SMBus bus buffer

6. Block diagram

PCA9510A

SDAIN

CONNECT

BACKPLANE-TO-CARD

CONNECTION

CONNECT

ENABLE

CONNECT

SDAOUT

100 kΩ

RCH1

1 VOLT

PRECHARGE

100 kΩ

RCH2

SCLIN

CONNECT

BACKPLANE-TO-CARD

CONNECTION

CONNECT

0.55V

0.45V

SCLOUT

0.5

µA

STOP BIT AND

BUS IDLE

0.55V

0.45V

20 pF

CONNECT

100

µs

DELAY

UVLO

READY

GND

UVLO

ENABLE

0.5 pF

CONNECT

002aab781

Fig 1. Block diagram of PCA9510A

PCA9510A_1

Product data sheet

Rev. 01 — 8 September 2005

3 of 23

Philips Semiconductors

PCA9510A

Hot swappable I

C-bus and SMBus bus buffer

7. Pinning information

7.1 Pinning

ENABLE

SCLOUT

SCLIN

GND

SDAOUT

SDAIN

READY

ENABLE

SCLOUT

SCLIN

GND

002aab783

SDAOUT

SDAIN

READY

PCA9510AD

002aab782

PCA9510ADP

Fig 2. Pin conﬁguration for SO8

Fig 3. Pin conﬁguration for TSSOP8

7.2 Pin description

Table 3:

Symbol

ENABLE

Pin description

Description

Chip enable. Grounding this input puts the part in a Low current (< 1

µA)

mode. It also disables the rise time accelerators, isolates SDAIN from

SDAOUT and isolates SCLIN from SCLOUT.

serial clock output to and from the SCL bus on the card

serial clock input to and from the SCL bus on the backplane

ground supply; connect this pin to a ground plane for best results

open-drain output which pulls LOW when SDAIN and SCLIN are

disconnected from SDAOUT and SCLOUT, and goes HIGH when the two

sides are connected

serial data input to and from the SDA bus on the backplane

serial data output to and from the SDA bus on the card

power supply

SCLOUT

SCLIN

GND

READY

SDAIN

SDAOUT

8. Functional description

Refer to

Figure 1 “Block diagram of PCA9510A”.

8.1 Start-up

An undervoltage and initialization circuit holds the parts in a disconnected state which

presents high-impedance to all SDAn and SCLn pins during power-up. A LOW on the

ENABLE pin also forces the parts into the low current disconnected state when the I

essentially zero. As the power supply is brought up and the ENABLE is HIGH or the part is

powered and the ENABLE is taken from LOW to HIGH, it enters an initialization state

where the internal references are stabilized and the precharge circuit is enabled. At the

end of the initialization state the ‘Stop Bit And Bus Idle’ detect circuit is enabled. With the

ENABLE pin HIGH long enough to complete the initialization state (t

) and remaining

HIGH when all the SDAn and SCLn pins have been HIGH for the bus idle time or when all

pins are HIGH and a STOP condition is seen on the SDAIN and SCLIN pins, SDAIN is

connected to SDAOUT and SCLIN is connected to SCLOUT. The 1 V precharge circuitry

PCA9510A_1

Product data sheet

Rev. 01 — 8 September 2005

4 of 23

Philips Semiconductors

PCA9510A

Hot swappable I

C-bus and SMBus bus buffer

is activated during the initialization and is deactivated when the connection is made. The

precharge circuitry pulls up the SDAIN and SCLIN input pins to 1 V through individual

100 kΩ nominal resistors. This precharges the pins to 1 V to minimize the worst case

disturbances that result from inserting a card into the backplane where the backplane and

the card are at opposite logic levels.

8.2 Connect circuitry

Once the connection circuitry is activated, the behavior of SDAIN and SDAOUT as well as

SCLIN and SCLOUT become identical with each acting as a bidirectional buffer that

isolates the input capacitance from the output bus capacitance while communicating the

logic levels. A LOW forced on either SDAIN or SDAOUT will cause the other pin to be

driven to a LOW by the part. The same is also true for the SCLn pins. Noise between

0.7V

and V

is generally ignored because a falling edge is only recognized when it

falls below 0.7V

with a slew rate of at least 1.25 V/µs. When a falling edge is seen on

one pin, the other pin in the pair turns on a pull-down driver that is referenced to a small

voltage above the falling pin. The driver will pull the pin down at a slew rate determined by

the driver and the load initially, because it does not start until the ﬁrst falling pin is below

0.7V

. The ﬁrst falling pin may have a fast or slow slew rate, if it is faster than the

pull-down slew rate then the initial pull-down rate will continue. If the ﬁrst falling pin has a

slow slew rate then the second pin will be pulled down at its initial slew rate only until it is

just above the ﬁrst pin voltage then they will both continue down at the slew rate of the

ﬁrst.

Once both sides are LOW they will remain LOW until all the external drivers have stopped

driving LOWs. If both sides are being driven LOW to the same value for instance, 10 mV

by external drivers, which is the case for clock stretching and is typically the case for

acknowledge, and one side external driver stops driving that pin will rise until the internal

driver pulls it down to the offset voltage. When the last external driver stops driving a

LOW, that pin will rise up and settle out just above the other pin as both rise together with

a slew rate determined by the internal slew rate control and the RC time constant. As long

as the slew rate is at least 1.25 V/µs, when the pin voltage exceeds 0.6 V for the

PCA9510A, the pull-down driver is turned off.

8.3 Maximum number of devices in series

Each buffer adds about 0.1 V dynamic level offset at 25

°C

with the offset larger at higher

temperatures. Maximum offset (V

offset

) is 0.150 V with a 10 kΩ pull-up resistor. The LOW

level at the signal origination end (master) is dependent upon the load and the only

speciﬁcation point is the I

C-bus speciﬁcation of 3 mA will produce V

< 0.4 V, although if

lightly loaded the V

may be

∼0.1

V. Assuming V

= 0.1 V and V

offset

= 0.1 V, the level

after four buffers would be 0.5 V, which is only about 0.1 V below the threshold of the

rising edge accelerator (about 0.6 V). With great care a system with four buffers may

work, but as the V

moves up from 0.1 V, noise or bounces on the line will result in ﬁring

the rising edge accelerator thus introducing false clock edges. Generally it is

recommended to limit the number of buffers in series to two, and to keep the load light to

minimize the offset.

The PCA9510A (rise time accelerator is permanently disabled) and the PCA9512A (rise

time accelerator can be turned off) are a little different with the rise time accelerator turned

off because the rise time accelerator will not pull the node up, but the same logic that turns

PCA9510A_1

Product data sheet

Rev. 01 — 8 September 2005

5 of 23