PCA9673
Remote 16-bit I/O expander for Fm+ I
2
C-bus with interrupt and
reset
Rev. 01 — 1 February 2007
Product data sheet
1. General description
The PCA9673 provides general purpose remote I/O expansion for most microcontroller
families via the two-line bidirectional bus (I
2
C-bus) and is a part of the Fast-mode Plus
family.
The PCA9673 is a drop in upgrade for the PCF8575 providing higher Fast-mode Plus
(Fm+) I
2
C-bus speeds (1 MHz versus 400 kHz) so that the output can support PWM
dimming of LEDs, higher I
2
C-bus drive (30 mA versus 3 mA) so that many more devices
can be on the bus without the need for bus buffers, higher total package sink capacity
(400 mA versus 100 mA) that supports having all 25 mA LEDs on at the same time and
more device addresses (16 versus 8) are available to allow many more devices on the bus
without address conflicts.
The difference between the PCA9673 and the PCF8575 is that the A2 address pin is
replaced by a RESET input on the PCA9673.
The device consists of a 16-bit quasi-bidirectional port and an I
2
C-bus interface. The
PCA9673 has a low current consumption and includes latched outputs with 25 mA high
current drive capability for directly driving LEDs.
It also possesses an interrupt line (INT) which can be connected to the interrupt logic of
the microcontroller. By sending an interrupt signal on this line, the remote I/O can inform
the microcontroller if there is incoming data on its ports without having to communicate via
the I
2
C-bus.
The internal Power-On Reset (POR), hardware reset pin (RESET) or software reset
sequence initializes the I/Os as inputs.
2. Features
I
I
I
I
I
I
I
I
I
I
1 MHz I
2
C-bus interface
Compliant with the I
2
C-bus Fast and Standard modes
SDA with 30 mA sink capability for 4000 pF buses
2.3 V to 5.5 V operation with 5.5 V tolerant I/Os
16-bit remote I/O pins that default to inputs at power-up
Latched outputs with 25 mA sink capability for directly driving LEDs
Total package sink capability of 400 mA
Active LOW open-drain interrupt output
16 programmable slave addresses using 2 address pins
Readable device ID (manufacturer, device type, and revision)
NXP Semiconductors
PCA9673
Remote 16-bit I/O expander for Fm+ I
2
C-bus with interrupt and reset
I
Low standby current
I
−40 °C
to +85
°C
operation
I
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I
Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA
I
Packages offered: SO24, SSOP24, QSOP24, TSSOP24, HVQFN24, DHVQFN24
3. Applications
I
I
I
I
I
I
I
I
LED signs and displays
Servers
Industrial control
Medical equipment
PLCs
Cellular telephones
Gaming machines
Instrumentation and test measurement
4. Ordering information
Table 1.
Ordering information
Topside
mark
PCA9673D
PCA9673
Package
Name
SO24
SSOP24
[1]
Description
plastic small outline package; 24 leads; body width 7.5 mm
plastic shrink small outline package; 24 leads;
body width 3.9 mm; lead pitch 0.635 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
Version
SOT137-1
SOT556-1
SOT355-1
SOT815-1
SOT616-1
Type number
PCA9673D
PCA9673DB
PCA9673DK
PCA9673PW
PCA9673BQ
PCA9673BS
PCA9673DB SSOP24
plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1
PCA9673PW TSSOP24
9673
9673
DHVQFN24 plastic dual in-line compatible thermal enhanced very thin quad
flat package; no leads; 24 terminals; body 3.5
×
5.5
×
0.85 mm
HVQFN24
plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 4
×
4
×
0.85 mm
[1]
Also known as QSOP24.
PCA9673_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 1 February 2007
2 of 33
NXP Semiconductors
PCA9673
Remote 16-bit I/O expander for Fm+ I
2
C-bus with interrupt and reset
5. Block diagram
PCA9673
INT
AD0
AD1
P00 to P07
P10 to P17
INTERRUPT
LOGIC
LP FILTER
SCL
SDA
INPUT
FILTER
I
2
C-BUS
CONTROL
SHIFT
REGISTER
16 BITS
I/O
PORT
RESET
V
DD
V
SS
POWER-ON
RESET
write pulse
read pulse
002aac300
Fig 1. Block diagram of PCA9673
write pulse
I
trt(pu)
data from Shift Register
D
FF
CI
S
power-on reset
D
FF
read pulse
CI
S
Q
Q
100
µA
I
OH
V
DD
I
OL
P00 to P07
P10 to P17
V
SS
data to Shift Register
002aab631
to interrupt logic
Fig 2. Simplified schematic diagram of P00 to P17
PCA9673_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 1 February 2007
3 of 33
NXP Semiconductors
PCA9673
Remote 16-bit I/O expander for Fm+ I
2
C-bus with interrupt and reset
6. Pinning information
6.1 Pinning
INT
AD1
RESET
P00
P01
P02
P03
P04
P05
1
2
3
4
5
6
7
8
9
24 V
DD
23 SDA
22 SCL
21 AD0
20 P17
19 P16
18 P15
17 P14
16 P13
15 P12
14 P11
13 P10
002aac301
INT
AD1
RESET
P00
P01
P02
P03
P04
P05
1
2
3
4
5
6
7
8
9
24 V
DD
23 SDA
22 SCL
21 AD0
20 P17
19 P16
18 P15
17 P14
16 P13
15 P12
14 P11
13 P10
002aac302
PCA9673D
PCA9673PW
P06 10
P07 11
V
SS
12
P06 10
P07 11
V
SS
12
Fig 3. Pin configuration for SO24
Fig 4. Pin configuration for TSSOP24
INT
AD1
RESET
P00
P01
P02
P03
P04
P05
1
2
3
4
5
6
7
8
9
24 V
DD
23 SDA
22 SCL
21 AD0
20 P17
19 P16
18 P15
17 P14
16 P13
15 P12
14 P11
13 P10
002aac303
INT
AD1
RESET
P00
P01
P02
P03
P04
P05
1
2
3
4
5
6
7
8
9
24 V
DD
23 SDA
22 SCL
21 AD0
20 P17
19 P16
18 P15
17 P14
16 P13
15 P12
14 P11
13 P10
002aac304
PCA9673DK
PCA9673DB
P06 10
P07 11
V
SS
12
P06 10
P07 11
V
SS
12
Fig 5. Pin configuration for SSOP24
(QSOP24)
Fig 6. Pin configuration for SSOP24
PCA9673_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 1 February 2007
4 of 33
NXP Semiconductors
PCA9673
Remote 16-bit I/O expander for Fm+ I
2
C-bus with interrupt and reset
terminal 1
index area
24 RESET
AD1
RESET
P00
18 AD0
17 P17
16 P16
15 P15
14 P14
13 P13
P10 10
P11 11
P12 12
7
8
9
P01
P02
P03
P04
P05
2
3
4
5
6
7
8
9
24 V
DD
23 SDA
22 SCL
21 AD0
20 P17
19 P16
18 P15
17 P14
16 P13
15 P12
14 P11
P10 13
20 SDA
23 AD1
terminal 1
index area
P00
P01
P02
P03
P04
P05
1
2
3
4
5
6
19 SCL
21 V
DD
22 INT
PCA9673BQ
PCA9673BS
P06 10
P07 11
V
SS
12
P06
P07
V
SS
002aac305
1
INT
002aac306
Transparent top view
Transparent top view
Fig 7. Pin configuration for HVQFN24
Fig 8. Pin configuration for DHVQFN24
6.2 Pin description
Table 2.
Symbol
Pin description
Pin
SO24, SSOP24,
TSSOP24, DHVQFN24
INT
AD1
RESET
P00
P01
P02
P03
P04
P05
P06
P07
V
SS
P10
P11
P12
P13
P14
P15
P16
P17
AD0
PCA9673_1
Description
HVQFN24
22
23
24
1
2
3
4
5
6
7
8
9
[1]
10
11
12
13
14
15
16
17
18
interrupt output (active LOW)
address input 1
reset input (active LOW)
quasi-bidirectional I/O 00
quasi-bidirectional I/O 01
quasi-bidirectional I/O 02
quasi-bidirectional I/O 03
quasi-bidirectional I/O 04
quasi-bidirectional I/O 05
quasi-bidirectional I/O 06
quasi-bidirectional I/O 07
supply ground
quasi-bidirectional I/O 10
quasi-bidirectional I/O 11
quasi-bidirectional I/O 12
quasi-bidirectional I/O 13
quasi-bidirectional I/O 14
quasi-bidirectional I/O 15
quasi-bidirectional I/O 16
quasi-bidirectional I/O 17
address input 0
© NXP B.V. 2007. All rights reserved.
1
2
3
4
5
6
7
8
9
10
11
12
[1]
13
14
15
16
17
18
19
20
21
Product data sheet
Rev. 01 — 1 February 2007
5 of 33
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