Features
H
6.6 SPEC int 95, 5.5 SPECfp95 @ 266 MHz (estimated)
H
Superscalar 603e core
H
Integer unit (IU), floating-point unit (FPU) (user enabled or disabled), load/
store unit (LSU), system register unit (SRU), and a branch processing unit
(BPU).
H
16-Kbyte instruction cache
H
16-Kbyte data cache
H
Lockable L1 caches-entire cache or on a per-way basis up to 3 of 4 ways.
H
Dynamic power management.
H
High-bandwidth bus (32/64 bits data bus) to DRAM.
H
Supports 1-Mbyte to 1-Gbyte DRAM memory.
H
32-bit PCI interface operating up to 66 MHz.
H
PCI 2.1-compliant, 5.0 V tolerance
H
Fint MAX = 250 MHz (tbc).
H
FBus MAX = 66 MHz (tbc)
PC8240
Integrated
Processor
Family
Preliminary
specification
alpha SITE
Description
The PC8240 combines a PowerPC
TM
603e core microprocessor with a PCI bridge. The
PC8240’s PCI support will allow system designers to rapidly design systems using peripherals
already designed for PCI and the other standard interfaces. The PC8240 also integrates a high-
performance memory controller which supports various types of DRAM and ROM. The PC8240
is the first of a family of products that provide system level support for industry standard inter-
faces with a PowerPC microprocessor core.
The peripheral logic integrates a PCI bridge, memory controller, DMA controller, EPIC interrupt
controller, I
2
O controller, and an I
2
C controller. The 603e core is a full-featured, high-perfor-
mance processor with floating-point support, memory management, 16-Kbyte instruction
cache, 16-Kbyte data cache, and power management features. The integration reduces the
overall packaging requirements and the number of discrete devices required for an embedded
system.
The PC8240 contains an internal peripheral logic bus that interfaces the 603e core to the periph-
eral logic. The core can operate at a variety of frequencies, allowing the designer to trade off
performance for power consumption. The 603e core is clocked from a separate PLL, which is
referenced to the peripheral logic PLL. This allows the microprocessor and the peripheral logic
block to operate at different frequencies, while maintaining a synchronous bus interface. The
interface uses a 64- or 32-bit data bus (depending on memory data bus width) and a 32-bit
address bus along with control signals that enable the interface between the processor and
peripheral logic to be optimized for performance. PCI accesses to the PC8240’s memory space
are passed to the processor bus for snooping purposes when snoop mode is enabled.
The PC8240’s features serve a variety of embedded applications. In this way, the 603e core and
peripheral logic remain general-purpose. The PC8240 can be used as either a PCI host or an
agent controller.
SCREENING/QUALITY/PACKAGING
This product is manufactured in full compliance with :
H
Upscreening based upon TCS standards.
H
Full military temperature range
(T
c
= 55°C, T
c
= +125°C)
H
Industrial temperature range
(T
c
= -40°C, T
c
= +110°C)
H
Core power supply :
. 2.5 +/- 5 % V (L-Spec for 200 MHz)
. 2.50 V to 2.75 V (R-Spec for 250 MHz) (tbc)
H
I/O power supply : 3.0 to 3.6 V
H
352 Tape Ball Grid Array (TBGA).
TP suffix
TBGA352
Tape Ball Grid Array
July 2000
1/44
SUMMARY
A. GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1. BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. PINOUT LISTINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
B. DETAILED SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1. SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2. APPLICABLE DOCUMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3. REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2. Design and construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.1. Terminal connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4. Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5. Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5.1. Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5.2. Thermal Management Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5.3. Internal Package Conduction Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.4. Heat Sink Selection Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6. Power consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.7. Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4. ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1. Static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2. Dynamic Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2.1. Clock AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.2. Input AC Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2.3. Output AC Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2.4. I2C AC Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.2.5. EPIC Serial Interrupt Mode AC Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2.6. IEEE 1149.1 (JTAG) AC Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5. PREPARATION FOR DELIVERY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1. Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2. Certificate of compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6. HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1. Package description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.1. Package Parameters for the PC8240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.2. Pin Assignments and Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.2. PLL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3. System Design Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3.1. PLL Power Supply Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3.2. Power Supply Voltage Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3.3. Power Supply Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3.4. Decoupling Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3.5. Connection Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3.6. Pull up/Pull down Resistor Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.3.7. JTAG Configuration Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7. DEFINITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8. DIFFERENCES WITH COMMERCIAL PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9. ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2/44
PC8240
PC8240
A. GENERAL DESCRIPTION
1. BLOCK DIAGRAM
The PC8240 integrated processor is comprised of a peripheral logic block and a 32-bit superscalar PowerPC 603e core, as shown in
Figure 1.
PC8240
Additional features:
•
JTAG/COP interface
•
Power management
603e Processor Core Block
Processor
PLL
(64 bit) Two–instruction fetch
Branch
Processing
Instruction Unit
Unit
(BPU)
(64–bit) Two–instruction dispatch
System
Register
Unit
(SRU)
Integer
Unit
(IU)
Load/Store
Unit
(LSU)
Floating–
Point
Unit
(FPU)
Data
MMU
16–Kbyte
Data
Cache
64 bit
Instruction
MMU
16–Kbyte
Instruction
Cache
Peripheral Logic
Bus
Peripheral Logic Block
Message
Controller
(I2O)
Address
(32 bit)
Data (64 bit)
Data Path
ECC Controller
Data Bus
(32– or 64–bit)
with 8–bit Parity
or ECC
Memory/ROM/PortX
Address and Control
DMA
Controller
Central
Control
Unit
Configuration
Registers
Memory
Controller
I2C
I2C
Controller
EPIC
Interrupt
Controller
/Timers
PCI Bus
Interface Unit
Address
Translator
PCI
Arbiter
DLL
Peripheral Logic
PLL
Fanout
Buffers
5 IRQs/
16 Serial
Interrupts
SDRAM
Clocks
PCI
Clock In
PCI Bus
Clocks
32–Bit
PCI Interface
Five
Request/Grant
Pairs
Oscillator
Input
Figure 1: Block Diagram
3/44
2. PINOUT LISTINGS
Table 1 provides the pinout listing for the PC8240, 352 TBGA package.
Table 1. PC8240 Pinout Listing
Signal Name
Package Pin Number
Pin Type
Power
Supply
Output Driver Type
Notes
PCI Interface Signals
C/BE[0–3]
DEVSEL
FRAME
IRDY
LOCK
AD[0–31]
A25 F23 K23 P25
H26
J24
K25
J26
C22 D22 B22 B23 D19 B24 A24
B26 A26 C26 D25 D26 E23 E25
E26 F24 L26 L25 M25 M26 N23
N25 N26 R26 R25 T26 T25 U23
U24 U26 U25 V25
G25
V26 W23 W24 W25
W26
AB26 AA25 AA26 Y25
Y26
G26
F26
H25
K26
AC26
P26
I/O
I/O
I/O
I/O
Input
I/O
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
DRV_PCI
DRV_PCI
DRV_PCI
DRV_PCI
—
DRV_PCI
6,15
8,15
8,15
8,15
8
6,15
PAR
GNT[0–3]
GNT4/DA5
REQ[0–3]
REQ4/DA4
PERR
SERR
STOP
TRDY
INTA
IDSEL
I/O
Output
Output
Input
Input
I/O
I/O
I/O
I/O
Output
Input
Memory Interface Signals
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
OVdd
DRV_PCI
DRV_PCI
DRV_PCI
—
—
DRV_PCI
DRV_PCI
DRV_PCI
DRV_PCI
DRV_PCI
—
15
6,15
7,15
6,12
12
8,15,18
8,15,16
8,15
8,15
15,16
—
MDL[0–31]
AD17 AE17 AE15 AF15 AC14
AE13 AF13 AF12 AF11 AF10 AF9
AD8 AF8 AF7 AF6 AE5 B1 A1 A3
A4 A5 A6 A7 D7 A8 B8 A10 D10
A12 B11 B12 A14
AC17 AF16 AE16 AE14 AF14
AC13 AE12 AE11 AE10 AE9 AE8
AC7 AE7 AE6 AF5 AC5 E4 A2 B3
D4 B4 B5 D6 C6 B7 C9 A9 B10
A11 A13 B13 A15
I/O
Gvdd
DRV_MEM_DATA
5,6,13
MDH[0–31]
I/O
Gvdd
DRV_MEM_DATA
6,13
4/44
PC8240
PC8240
Power
Supply
Gvdd
Gvdd
Gvdd
Gvdd
Gvdd
Gvdd
Signal Name
CAS/DQM[0–7]
RAS/CS[0–7]
FOE
RCS0
RCS1
SDMA[11 – 0]
Package Pin Number
AB1 AB2 K3 K2 AC1 AC2 K1 J1
Y4 AA3 AA4 AC4 M2 L2 M1 L1
H1
N4
N2
N1 R1 R2 T1 T2 U4 U2 U1 V1 V3
W1 W2
P1
P2
AF3 AE3 G4 E2 AE4 AF4 D2 C2
AD1
AD2
H2
AA1
Y1
Pin Type
Output
Output
I/O
I/O
Output
Output
Output Driver Type
DRV_MEM_ADDR
DRV_MEM_ADDR
DRV_MEM_ADDR
DRV_MEM_ADDR
DRV_MEM_ADDR
DRV_MEM_ADDR
Notes
6
6
3,4
3,4
6,14
SDMA12/SDBA1
SDBA0
PAR[0–7]
SDRAS
SDCAS
CKE
WE
AS
Output
Output
I/O
Output
Output
Output
Output
Output
EPIC Control Signals
Gvdd
Gvdd
Gvdd
Gvdd
Gvdd
Gvdd
Gvdd
Gvdd
DRV_MEM_ADDR
DRV_MEM_ADDR
DRV_MEM_DATA
DRV_MEM_ADDR
DRV_MEM_ADDR
DRV_MEM_ADDR
DRV_MEM_ADDR
DRV_MEM_ADDR
14
—
6,13,14
3
3
3,4
—
3,4
IRQ_0 / S_INT
IRQ_1 / S_CLK
IRQ_2 / S_RST
IRQ_3 / S_FRAME
IRQ_4/ L_INT
C19
B21
AC22
AE24
A23
Input
I/O
I/O
I/O
I/O
I
2
C Control Signals
Ovdd
Ovdd
Ovdd
Ovdd
Ovdd
—
DRV_PCI
DRV_PCI
DRV_PCI
DRV_PCI
—
—
—
—
—
SDA
SCL
AE20
AF21
I/O
I/O
Clock Out Signals
Ovdd
Ovdd
DRV_STD
DRV_STD
10,16
10,16
PCI_CLK [0–3]
PCI_CLK4/DA3
PCI_SYNC_OUT
PCI_SYNC_IN
SDRAM_CLK [0–3]
AC25 AB25 AE26 AF25
AF26
AD25
AB23
D1 G1 G2 E1
Output
Output
Output
Input
Output
GVdd
GVdd
GVdd
GVdd
GVdd
DRV_PCI_CLK
DRV_PCI_CLK
DRV_PCI_CLK
—
DRV_MEM_ADDR
6
—
—
—
6
5/44
