Input signal level detect and squelch for each channel
ÎÎ
OOB support
ÎÎ
Low Power (100mW per Channel)
ÎÎ
Stand-by Mode – Power Down State
ÎÎ
DD
Operating Range: 1.5V to 1.8V
V
ÎÎ
Industrial Operating Temperature Range: -40°C to 85°C
ÎÎ
Packaging:
Description
Pericom Semiconductor’s PI2EQX3421 is a low power, signal
ReDriver. The device provides programmable equalization, to
optimize performance over a variety of physical mediums by
reducing Inter-Symbol Interference. PI2EQX3421 supports two
100-Ohm Differential CML data I/O’s between the Protocol
ASIC to a switch fabric, across a backplane, or to extend the sig-
nals across other distant data pathways on the user’s platform.
The integrated equalization circuitry provides flexibility with
signal integrity of the signal input to ReDriver.
A low-level input signal detection and output squelch function is
provided for each channel. Each channel operates fully indepen-
dently. When the channels are enabled (CE=1) and operating,
that channels input signal level (on XIN+/-) determines whether
the output is enabled. If the input signal level of the channel
falls below the active threshold level (Vth-) then the outputs are
driven to the common mode voltage.
In addition to signal conditioning, Pericom’s PI2EQX3421 also
provides power management Stand-by mode operated by the
Chip Enable (CE) pin.
— 28-TQFN (3.5x 5.5mm)
Block Diagram
SIGNAL
DETECT
Pin Description (Top Side View)
FA_ES
F_EQ
F_SD
FA_OUT+
F_IN+
EQUALIZER
F_IN-
FA_ES
FB_OUT+
FB_OUT-
FB_ES
FA_OUT-
RA_EQ
CE
F_EQ
RA_SD
F_SD
VDD
F_IN+
F_IN-
RA_SD
SIGNAL
DETECT
LOGIC
EQUALIZER
SIGNAL
DETECT
1 28 27 26 25 24
23
2
22
3
21
4
5
6
7
8
GND
20
19
18
17
16
FA_OUT+
FA_OUT-
VDD
RA_IN+
RA_IN-
FB_OUT+
FB_OUT-
VDD
RB_IN+
RB_IN-
RA_IN+
RA_IN-
RA_EQ
R_OUT+
R_OUT-
R_ES
RB_SD
SIGNAL
DETECT
VDD
VDD
R_OUT+
R_OUT-
RB_SD
9
11 12 13 14
15
10
RB_EQ
FB_ES
CH_SEL
R_ES
CH_SEL
TEST#
CE
CONTROL
LOGIC
RB_IN+
EQUALIZER
RB_IN-
RB_EQ
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PS8972D
12/18/12
3.2Gbps, 1:2 Port Switch, SATA2/SAS ReDriver™
Pin Description
Pin #
25
14
28
4
5
2
26
24
23
12
19
18
Center Pad
13
27
21
20
1
11
16
15
10
8
9
3,6,7,17,22
PI2EQX3421
Pin Name
CE
CH_SEL
F_EQ
F_IN+
F_IN-
F_SD
FA_ES
FA_OUT+
FA_OUT-
FB_ES
FB_OUT+
FB_OUT-
GND
R_ES
RA_EQ
RA_IN+
RA_IN-
RA_SD
RB_EQ
RB_IN+
RB_IN-
RB_SD
R_OUT+
R_OUT-
VDD
Type
Input
Input
Input
Input
Output
Input
Output
Input
Output
GND
Input
Input
Input
Output
Input
Input
Output
Output
Power
Description
Chip Enable "high" provides normal operation. "Low" for power down mode.
With internal 50K-Ohm pull-up resistor.
Channel Select "high" selects path A. "Low" selects path B. With internal 50K-
Ohm pull-up resistor.
Selection pin for equalizer of Fin. "Low" means 2.5dB, "high" means 6.5dB. With
internal 50K-Ohm pull-up resistor.
CML input channel F with internal 50-Ohm pull down.
Channel Fin Signal detector output. Provides "high" when a signal is detected.
"High" means FA_OUT operates to the SATA i/m standard. "Low" means FA_
OUT support SATAx standard. With internal 50K-Ohm pull-up resistor.
CML output channel FA with internal 50-Ohm pull up.
"High" means FB_OUT operates to the SATA i/m standard. "Low" means FB_
OUT support SATAx standard. With internal 50K-Ohm pull-up resistor.
CML output channel FB with internal 50-Ohm pull up.
Supply ground.
"High" means Rout operates to the SATA i/m standard. "Low" means Rout sup-
port SATAx standard. With internal 50K-Ohm pull-up resistor.
Selection pin for equalizer of RA_IN. "Low" means 2.5dB, "high" means 6.5dB.
With internal 50K-Ohm pull-up resistor.
CML input channel RA with internal 50-Ohm pull down.
Signal detector for Channel RA_IN. Provides "high" when signal is detected.
Selection pin for equalizer of RB_IN. "Low" means 2.5dB, "high" means 6.5dB.
With internal 50K-Ohm pull-up resistor.
CML input channel RB with internal 50-Ohm pull down.
Signal detector for Channel RB_IN. Provides "high" when signal is detected.
CML output channel R with internal 50-Ohm pull up.
Positive Supply Voltage, 1.5V to 1.8V (±0.1V)
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PS8972D
12/18/12
3.2Gbps, 1:2 Port Switch, SATA2/SAS ReDriver™
Equalizer Selection
x_EQ
0
1
PI2EQX3421
Compliance Channel @ 1.6 GHz
1.5dB ± 1.0dB
5.5dB ± 1.0dB
Output CML Buffer
CE
0
1
1
1
1
CH_SEL
X
0
0
1
1
X_ES
X
0
1
0
1
FA_OUT
VDD
VDD
VDD
VDD-0.6V
VDD-0.3V
FB_OUT
VDD
VDD-0.6V
VDD-0.3V
VDD
VDD
R_OUT
VDD
VDD-0.6V
VDD-0.3V
VDD-0.6V
VDD-0.3V
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PS8972D
12/18/12
3.2Gbps, 1:2 Port Switch, SATA2/SAS ReDriver™
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Storage Temperature.......................................................... –65°C to +150°C
Supply Voltage to Ground Potential...................................–0.5V to +2.5V
DC SIG Voltage .......................................................... –0.5V to VDD +0.5V
Current Output ................................................................-25mA to +25mA
Power Dissipation Continous ..........................................................500mW
Operating Temperature ........................................................... -40 to +85°C
Note:
Stresses greater than those listed under MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this specification is not implied. Ex-
posure to absolute maximum rating conditions for extended
periods may affect reliability.
PI2EQX3421
AC/DC Electrical Characteristics
(V
DD
= 1.4V to 1.9V)
Symbol
Parameter
Conditions
P
STANDBY
P
ACTIVE
T
pd
T
SW
Supply Power
Active Supply Power
Latency
Switch time, idle to active
CE = LVCMOS Low
CE = LVCMOS High
Input to Output
CH_Sel toggles
Min.
Typ.
Max.
1
0.25
Units
mW
W
ns
ns
1.0
50
CML Receiver Input
V
RX-DIFFP-P
V
RX-CM-ACP
Z
RX-DC
Z
RX-DIFF-DC
Differential Input Peak-to-
peak Voltage
AC Peak Common Mode
Input Voltage
DC Input Impedance
DC Differential Input
Impedance
40
85
50
100
0.200
150
60
115
Ohm
V
mV
Equalization
J
RS
J
RM
V
TH
T
EN
Notes
Residual Jitter
(1,2)
Random Jitter
(1,2)
Threshold
Enable/disable time
Total Jitter
1.5
CE = 1
65
(3)
0.3
Ulp-p
psrms
Signal Detector Performance
200
(3)
mVppd
16
ns
1. K28.7 pattern is applied differentially at point A as shown in Figure 1.
2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 × RJ + DJ) where RJ is random RMS jitter and DJ is maximum deterministic jitter.
Signal source is a K28.5 ± pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or equivalent for random jitter test. Re-
sidual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or its equivalent. The deterministic jitter at point B must
be from media-induced loss, and not from clock source modulation. JItter is measured at 0V at point C of Figure 1.
3. Using Compliance test at 1.5Gbps and 3Gbps. Also using OOB (OOB is formed by ALIGNp primitive or D24.3) test patterns at 1.5Gbps. The ALIGN primitive
(K28.5+D10.2+D27.3 = 0011111010+0101010101+0010011100). The D24.3 = 00110011001100110011
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13-0021
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PS8972D
12/18/12
3.2Gbps, 1:2 Port Switch, SATA2/SAS ReDriver™
AC/DC Electrical Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
CML Transmitter Output (100-Ohm differential)
V
TX-DIFFP-P
V
TX-C
t
F
, t
R
t
F
-t
R /
t
F
+t
R
Z
OUT
Z
TX-DIFF-DC
C
TX
Differential Peak-to-peak Output x_ES=1
Voltage
(1)
V
TX-DIFFP-P
x_ES=0
= 2*|V
TX-D+
- V
TX-D-
|
Common-Mode Voltage
(1)
| V
TX-D+
+ V
TX-D-
| / 2
Transition Time
Transition Mismatch Time
Output resistance
DC Differential TX Impedance
AC Coupling Capacitor
x_ES=1
x_ES=0
20% to 80%
20% to 80%
Single ended
80
0.3
0.65 ×
V
DD
0.35 ×
V
DD
250
500
I
OH
= 4mA
I
OL
= 4mA
V
DD
-
0.45
0.4
50
100
4.7
120
12
400
800
V
DD
-0.6
V
DD
-0.3
150
20
750
1300
mVppd
mV
ps
%
Ohm
Ohm
nF
PI2EQX3421
LVCMOS Control Pins
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
Note:
1. When x_ES=0, select SATAx standard. When x_ES=1, select SATAI/m standard.
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
DC Output Logic High
DC Output Logic Low
V
µA
V
FR4
Signal
Source
A
B
Pericom
PI2EQX3421
In
Out
C
SmA
Connector
30
IN
SmA
Connector
Figure 1. Test Condition Referenced in the Electrical Characteristic Table
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