PI6LC48L0201
2-Output LVDS Networking Clock Generator
Features
ÎÎ
Two differential LVDS output pairs
ÎÎ
Selectable crystal oscillator interface or LVCMOS/LVTTL
Description
The PI6LC48L0201 is a 2-output LVDS synthesizer optimized to
generate Ethernet reference clock frequencies and is a member
of Pericom’s HiFlex family of high performance clock solutions.
Using a 25MHz crystal, the most popular Ethernet frequencies
can be generated based on the settings of 2 frequency select pins.
The PI6LC48L0201 uses Pericom’s proprietary low phase noise
PLL technology to achieve ultra low phase jitter, so it is ideal for
Ethernet interface in all kind of systems.
single-ended clock input
125MHz, 156.25MHz
ÎÎ
Supports the following output frequencies: 62.5MHz,
ÎÎ
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 0.2ps (typical)
(12kHz – 20MHz): 0.32ps (typical)
ÎÎ
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
ÎÎ
Full 3.3V or 2.5V supply modes
ÎÎ
Commercial and industrial ambient operating temperature
ÎÎ
Available in lead-free package: 20-TSSOP
Applications
ÎÎ
Networking systems
Block Diagram
XTAL_IN
XTAL_OUT
Ref_IN
OSC
PFD
VCO
/N
CLK0
CLK0#
IN_SEL
M
PLL_ByPass
N_SEL[0:1]
CLK1
CLK1#
M_reset
13-0115
1
www.pericom.com
PI6LC48L0201
Rev. A
07/23/2013
2-Output LVDS Networking Clock Generator
Pin Configuration
NC
VDDO
CLK0
CLK0#
M_reset
PLL_ByPass
NC
VDDA
N_SEL0
VDD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDDO
CLK1
CLK1#
GND
NC
IN_SEL
Ref_IN
XTAL_IN
XTAL_OUT
N_SEL1
PI6LC48L0201
Pinout Table
Pin No.
1, 7, 16
2, 20
3,4
5
6
8
9, 11
10
12, 13
14
15
17
18, 19
Pin Name
NC
VDDO
CLK0, CLK0#
M_reset
PLL_ByPass
VDDA
VDD
XTAL_OUT,
XTAL_IN
Ref_IN
IN_SEL
GND
CLK1#,
CLK1
I/O Type
Power
Output
Input
Input
Power
Power
Crystal
Input
Input
Ground
Output
-
-
Pull-down
Description
No connection
Output Power Supply
LVDS Output clock 0
Master reset. “1”, CLK0CLK1 go to “low”, CLK0#/CLK1# go to
“high”; “0” outputs are enabled
Analog Power Supply
Core Power Supply
Crystal input and output
Pull-down PLL bypass select. “0” PLL is enabled, “1” PLL is bypassed
-
-
-
Pull-down Output frequency select
N_SEL0, N_SEL1 Input
Pull-down CMOS reference clock input
Pull-down “0” selects Crystal, “1” selects reference input
-
-
Ground
LVDS Output clock 1
13-0115
2
www.pericom.com
PI6LC48L0201
Rev. A
07/23/2013
2-Output LVDS Networking Clock Generator
Output Frequency Selection Table
Xtal Frequency
N_SEL1 N_SEL0
00
25
01
10
11
PI6LC48L0201
Output Frequency
156.25
125
62.5
Reserved
Typical Crystal Requirement
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance
(ESR)
Shunt Capacitance
Drive Level
22.4
Minimum
Typical
Fundamental
25
Maximum
27.2
50
7
1
Units
MHz
Ω
pF
mW
Recommended Crystal Specification
Pericom recommends:
a) FL2500047, SMD 3.2x2.5(4P), 25MHz, CL=18pF, +/-20ppm, http://www.pericom.com/pdf/datasheets/se/FL.pdf
b) FY2500091, SMD 5x3.2(4P), 25MHz, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf
13-0115
3
www.pericom.com
PI6LC48L0201
Rev. A
07/23/2013
2-Output LVDS Networking Clock Generator
Maximum Ratings
(Over operating free-air temperature range)
Storage Temperature.............................................. -65ºC to+155ºC
Ambient Temperature with Power Applied .........-40ºC to+85ºC
3.3V Analog Supply Voltage ......................................-0.5 to +3.6V
ESD Protection (HBM) ......................................................... 2000V
PI6LC48L0201
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
DC Electrical Characteristics
Power Supply DC Characterisitcs,
(T
A
= -40ºC to 85ºC)
Symbol
Parameter
Condition
Min
3.135
2.375
Typ
3.3
2.5
Max
3.465
2.625
105
98
26
26
55
55
Units
V
V
mA
mA
mA
V
DD
,
Core Supply Voltage
V
DDA
,
V
DDO
V
DD
,
Analog Supply Voltage
V
DDA
,
V
DDO
I
DD
I
DDA
I
DDO
Power Supply Current
Analog Supply Current
Output Supply Current
V
DD
=V
DDA
= V
DDO
= 3.3V +/-5%
V
DD
=V
DDA
= V
DDO
= 2.5V +/-5%
V
DD
=V
DDA
= V
DDO
= 3.3V +/-5%
V
DD
=V
DDA
= V
DDO
= 2.5V +/-5%
V
DD
=V
DDA
= V
DDO
= 3.3V +/-5%
V
DD
=V
DDA
= V
DDO
= 2.5V +/-5%
LVCMOS/LVTTL DC Characterisitcs,
(T
A
= -40ºC to 85ºC)
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Input Low Voltage
Condition
V
DD
= 3.3 V +/- 5%
V
DD
= 2.5 V +/- 5%
V
DD
= 3.3 V +/- 5%
V
DD
= 2.5 V +/- 5%
M_reset, PLL_ByPass, N_
SEL[0:1], IN_SEL, Ref_IN
V
DD
= VIN = 3.465V
M_reset, PLL_ByPass, N_
SEL[0:1], IN_SEL, Ref_IN
V
DD
= 3.465V,
V
IN
= 0V
Min
2
1.7
-0.3
-0.3
Typ
Max
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
I
IH
Input High Current
I
IL
Input Low Current
-5
µA
Pin Characterisitcs
Symbol
C
IN
Parameter
Input Capacitance
Condition
Min
Typ
4
51
Max
Units
pF
kΩ
R
PULLDOWNN
Pull down resistor
13-0115
4
www.pericom.com
PI6LC48L0201
Rev. A
07/23/2013
2-Output LVDS Networking Clock Generator
LVDS DC Characterisitcs,
(T
A
= -40ºC to 85ºC)
Symbol
V
OD
DV
OD
V
OS
DV
OS
PI6LC48L0201
Parameter
Differential Output Voltage
Change of V
OD
Output Offset Voltage
Change of V
OS
Condition
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.5V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.5V
V
DD
= 2.5V
Min
247
247
Typ
Max
454
454
Units
mV
mV
50
50
1.125
1.125
50
50
1.375
1.375
V
mV
AC Electrical Characteristics,
(T
A
= -40ºC to 85ºC)
Symbol
f
OUT
t
sk(o)
Parameter
Output Frequency
Output Skew
(1, 3)
Condition
N_SEL[1:0] = 00
N_SEL[1:0] = 01
N_SEL[1:0] = 10
Outputs @ same loading
156.25MHz,
(1.875MHz - 20MHz)
156.25MHz,
(12kHz - 20MHz)
Min.
140
112
56
Typ.
Max
170
136
68
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
50
0.2
0.32
0.2
0.31
0.4
0.5
400
48
52
t
jit(Ø)
RMS Phase Jitter,
(Random)
(2)
125MHz,
(1.875MHz - 20MHz)
125MHz,
(12kHz - 20MHz)
62.5MHz,
(1.875MHz - 20MHz)
62.5MHz,
(12kHz - 20MHz)
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
ps
%
Note:
1.
Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points.
2.
Please refer to the Phase Noise Plots.
3.
This parameter is defined in accordance with JEDEC Standard 65.
13-0115
5
www.pericom.com
PI6LC48L0201
Rev. A
07/23/2013
模拟与混合信号
