21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
1
2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LVTCH244
3.3V 8-Bit Buffers/Line Drivers
with 3-State Outputs
Product Features
•
Advanced low power CMOS design for 2.7V to 3.6V
Vcc operation
•
Supports 5V input/output tolerance in mixed signal mode
operation
•
Function compatible with LVT family of products
•
Balanced ±24mA output drive
•
Typical V
OLP
(Output Ground Bounce) < 0.8V at V
CC
=3.3V,
T
A
=25°C
•
I
off
and Power Up/Down 3-State support live insertion
•
Latch-up performance exceeds 200mA Per JESD78
•
Bus Hold on data inputs eliminates the need for external
pull-up/down resistors
•
ESD protection exceeds JESD 22
–
2000V Human-Body Model (A114-B)
–
200V Machine Model (A115-A)
•
Packaging:
–
20-pin 209-mil wide plastic SSOP (H)
–
20-pin 173-mil wide plastic TSSOP (L)
–
20-pin 300-mil wide plastic SOIC (S)
Product Description
The PI74LVTCH244 is a non-inverting 8-bit buffer and line driver
designed for low-voltage 2.7V to 3.6V V
CC
operation, with the
capability of interfacing to the 5V system environment. With its
balanced drive characteristics, this high-speed, low power device
provides low ground bounce and transmission line impedance
matching. This makes it ideal for driving on board buses and
transmission lines. The device can be used as two 4-bit buffers with
separate output enable (OE) inputs.
The PI74LVTCH244 has "Bus Hold" which retains the data input's
last valid logic state whenever the data input goes to high-imped-
ance, preventing "floating" inputs and eliminating the need for pul-
up/down resistors.
When Vcc is between 0 to 1.5V during power up or power down, the
outputs of the device are in the high-impedance state.
To ensure the high-impedance state above 1.5V, OE should be tied
to Vcc through a pullup resistor; the minimum value of the resistor
is determined by the current sinking capability of the driver.
The device fully supports live-insertion with its I
off
and power-up/
down 3-state. The I
off
circuitry disables the outputs when the
power is off, preventing the backflow of damaging current through
the device. Power-up/down 3-state places the outputs in the
high-impedance state during power up or power down, preventing
driver conflict.
Logic Block Diagram
1OE
1A1
1
2
18
2OE
1Y1
2A1
19
11
9
2Y1
1A2
4
16
1Y2
2A2
13
7
2Y2
1A3
6
14
1Y3
2A3
15
5
2Y3
1A4
8
12
1Y4
2A4
17
3
2Y4
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Truth Table
(1)
Inputs
xOE
L
L
H
Notes:
1. H = High Signal Level
L = Low Signal Level
X = Don’t Care or Irrelevant
Z = High Impedance
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LVTCH244
8-Bit Buffers/Line Drivers
with 3-State Outputs
Maximum Ratings
(Above which the useful life may be impaired.
For user guidelines, not tested.)
Supply voltage range, V
CC
.............................. –0.5V to +6.5V
Input voltage range, V
I
(1)
................................. –0.5V to +6.5V
Voltage range applied to any output in the
high-impedance or power-off state, V
O
(1)
........ –0.5V to +6.5V
Voltage range applied to any output in the
active state, V
O
(1,2)
.................................... –0.5V to V
CC
+0.5V
Input clamp current, I
IK
(V
I
<0) ..................................... –50mA
Output clamp current, I
OK
(V
O
<0) ............................... –50mA
Continous Output Current I
O
....................................... ±50mA
Continous Current through each V
CC
or GND pin ............... ±100mA
Package thermal impedance,
θ
JA
(2)
: package H ............ 81°C/W
package L ............ 84°C/W
package S ............ 84°C/W
Storage Temperature range, T
stg
..................... –65°C to 150°C
Notes:
Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
1. Input negative-voltage and output voltage ratings may be exceeded if the
input and output clamp current ratings are observed.
2. This value is limited to 6.5V maximum.
3. The package thermal impedance is calculated in accordance with
JESD 51.
Product Pin Description
Pin Name
xOE
xAx
xYx
GND
V
C C
Inputs
3- State Outputs
Ground
Power
De s cription
3- State Output Enable Inputs (Active LOW)
Product Pin Configuration
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
20-Pin
H, L, S
Outputs
xAx
H
L
X
xYx
H
L
Z
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LVTCH244
3.3V 8-Bit Buffers/Line Drivers
with 3-State Outputs
Recommended Operating Conditions
(1)
M in.
V
CC
V
IH
V
IL
V
I
V
O
Supply Voltage
High- level Input Voltage
Low- level Input Voltage
Input Voltage
Output Voltage
High or Low State
3- State
V
CC
= 2.7V
V
CC
= 3.0V to 3.6V
V
CC
= 2.7V
V
CC
= 3.0V to 3.6V
150
–40
85
Operating
V
CC
= 2.7V to 3.6V
V
CC
= 2.7V to 3.6V
0
0
0
2.7
2 .0
0. 8
5 .5
V
CC
5.5
–12
–24
12
24
10
ns/V
μ
s/V
°C
mA
V
M a x.
3 .6
Units
I
OH
High- level output current
I
O
L Low- level output current
Δ
t/
Δ
V Input transition rise or fall rate
Δ
t/
ΔV
CC
Power- up ramp rate
T
A
Operating free- air temperature
Notes:
1. All unused inputs must be held at V
CC
or GND to ensure proper device operation.
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LVTCH244
8-Bit Buffers/Line Drivers
with 3-State Outputs
DC Electrical Characteristics
(Over the Operating Range, T
A
= –40°C +85°C)
Parame te rs
V
IK
De s cription
Clamp Diode Voltage
V
CC
= 2.7V
V
CC
= 2.7V to 3.6V
V
OH
Output High Voltage
V
CC
= 2.7V
V
CC
= 3V
V
CC
= 2.7V to 3.6V
V
OL
Output Low Voltage
V
CC
= 2.7V
V
CC
= 3V
Control
Inputs
I
I
Input Leakage
Current
Data
Inputs
V
CC
= 0V to 3.6V
Te s t Conditions
I
I
= –18mA
I
OH
= –100
μA
I
OH
= –12mA
I
OH
= –12mA
I
OH
= –24mA
I
OL
= 100
μA
I
OL
= 12mA
I
OL
= 12mA
I
OL
= 24mA
V
I
= 0V to5.5V
V
I
= 5.5V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
I
I(HOLD)
Data Input Hold Current
Power Off Output
Leakage Current
3- State Output Leakage
Current
Power- Up 3- State
Current
Power- Down 3- State
Current
Quiescent Power Supply
Current
Increase in I
CC
V
CC
= 3V
V
CC
= 3.6V
(1)
I
OFF
I
OZ
I
OZPU
I
OZPD
I
CC
ΔI
CC
V
CC
= 0V
V
CC
= 2.7V to 3.6V
V
CC
= 0V to 1.5V
V
CC
= 1.5V to 0V
V
CC
= 2.7V to 3.6V
V
CC
= 3V to 3.6V
V
I
= 0.8V
V
I
= 2V
V
I
= 0 to 3.6V
V
I
or V
O
= 0V to 5.5V
V
O
= 0V to 5.5V
V
O
= 0.5V to 5.5V,
OE = don't care
V
O
= 0.5V to 5.5V,
OE = don't care
V
I
= V
CC
or GND
3.6V
≤
V
I
≤
5.5V
I
O
= 0
75
–75
± 500
±5
±5
±5
±5
100
200
μ
A
±5
V
CC
–0.2V
2 .2
2 .4
2 .2
0 .2
0 .4
0 .4
0.5 5
±5
V
M in.
M ax.
–1.2V
Units
One input at V
CC
- 0.6V
(2)
Other inputs at V
CC
or GND
Notes:
1. This is the maximum bus-hold dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
2. This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND.
06-0215
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LVTCH244
3.3V 8-Bit Buffers/Line Drivers
with 3-State Outputs
Capacitance
Parame te rs
C
IN
C
OUT
C
PD
De s cription
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
(2)
Te s t Conditions
V
CC
= 3.3V, V
I
= V
CC
or GND
V
CC
= 3.3V, V
O
= V
CC
or GND
V
CC
= 3.3V, V
I
= 0V or V
CC,
f =10 MHz
Typ.
(1)
3. 0
6. 2
28
pF
Units
Notes:
1. All typical values are measured at V
CC
= 3.3V, T
A
= 25°C.
2. C
PD
is defined as the value of the internal equivalent capacitance withic is derived from dynamic operating current consumption (I
CCD
) at no
output loading and operating at 50% duty cycle, C
PD
is related to I
CCD
dynamic operating current by the expression: I
CCD
=
(C
PD
)(V
CC
)(f
IN
)+(I
CC
static).
Switching Characteristics Over Operating Range
To
(Outp-
ut)
V
CC
= 3.3V ±0.3V
C
L
= 50pF, R
L
= 500-ohm
M in.
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SK(O)
Propagation Delay
A
Y
1. 0
1.0
1. 0
1.0
1.0
1.0
M ax.
5. 2
5. 2
5. 8
5. 8
4.6
4.6
0.5
V
CC
= 2.7V
C
L
= 50pF, R
L
= 500-ohm
M in.
1.0
1.0
1.0
1.0
1.0
1.0
M ax.
5 .8
5 .8
6 .8
6 .8
4.8
4.8
ns
Units
Parame te rs
De s cription
From
(Input)
Output Enable Time
OE
Y
Output Disable Time
Output to Output Skew
(1)
OE
Y
Notes:
1. Skew between any two outputs, switching in the same direction.
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