PIC12F6XX/16F6XX
PIC12F6XX/16F6XX
Memory Programming Specification
This document includes the
programming specifications for the
following device:
• PIC12F635
• PIC12F683
• PIC16F631
• PIC16F636
• PIC16F639
• PIC16F677
• PIC16F684
• PIC16F685
• PIC16F687
• PIC16F688
• PIC16F689
• PIC16F690
1.1
Hardware Requirements
PIC12F6XX/16F6XX devices require one power supply
for V
DD
(5.0V) and one for V
PP
(12.0V).
1.2
Program/Verify Mode
The Program/Verify mode for the PIC12F6XX/16F6XX
devices allow programming of user program memory,
data memory, user ID locations and the Configuration
Word.
Programming and verification can take place on any
memory region, independent of the remaining regions.
This allows independent programming of program and
data memory regions. Therefore, unprotected data
memory can be reprogrammed and protected without
losing the content in the program memory.
1.0
PROGRAMMING THE
PIC12F6XX/16F6XX DEVICES
The PIC12F6XX/16F6XX devices are programmed
using a serial method. The Serial mode will allow the
PIC12F6XX/16F6XX devices to be programmed while
in the user’s system. This programming specification
applies to the PIC12F6XX/16F6XX devices in all
packages.
TABLE 1-1:
Pin Name
PIN DESCRIPTIONS IN PROGRAM/VERIFY MODE
During Programming
Function
Pin Type
I
I/O
P
(1)
P
P
Pin Description
Clock input – Schmitt Trigger input
Data input/output – Schmitt Trigger input
Program Mode Select
Power Supply
Ground
GP1/RA1
GP0/RA0
MCLR
V
DD
V
SS
ICSPCLK
ICSPDAT
Program/Verify mode
V
DD
V
SS
Legend:
I = Input, O = Output, P = Power
Note 1:
In the PIC12F6XX/16F6XX, the programming high voltage is internally generated. To activate the
Program/Verify mode, high voltage needs to be applied to MCLR input. Since the MCLR is used for a level
source, MCLR does not draw any significant current.
2009-2015 Microchip Technology Inc.
DS40001204J-page 1
PIC12F6XX/16F6XX
FIGURE 1-1:
PDIP, SOIC, DFN
8-PIN DIAGRAM FOR PIC12F635/683
PIC12F635/683
V
DD
GP5/OSC1/CLKIN
GP4/OSC2/CLKOUT
GP3/MCLR/V
PP
1
2
3
4
8
7
6
5
V
SS
GP0/ICSPDAT
GP1/ICSPCLK
GP2
FIGURE 1-2:
14-PIN DIAGRAM FOR PIC16F636/684/688
PDIP, SOIC, TSSOP
FIGURE 1-3:
QFN
16-PIN DIAGRAMS FOR PIC16F636/684/688
V
DD
PIC16F636/684/688
V
DD
RA5/OSC1/CLKIN
RA4/OSC2/CLKOUT
RA3/MCLR/V
PP
RC5
RC4
RC3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
SS
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RC0
RC1
RC2
16
15
14
RC2 7
RA5/OSC1/CLKIN
RA4/OSC2/CLKOUT
RA3/MCLR/V
PP
RC5
1
2
3
4
RC4 5
RC3 6
PIC16F636/684/688
13
V
SS
12 RA0/ICSPDAT
11 RA1/ICSPCLK
10 RA2
9 RC0
RC1 8
NC
NC
DS40001204J-page 2
2009-2015 Microchip Technology Inc.
PIC12F6XX/16F6XX
FIGURE 1-4:
20-PIN DIAGRAMS
V
DD
RA5/OSC1/CLKIN
RA4/OSC2/CLKOUT
RA3/MCLR/V
PP
RC5
RC4
RC3
V
DDT
LCZ
LCY
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
SS
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RC0
RC1
RC2
V
SST
LCCOM
LCX
PDIP, SOIC
(1)
, TSSOP
V
DD
RA5/OSC1/CLKIN
RA4/OSC2/CLKOUT
RA3/MCLR/V
PP
RC5
RC4
RC3
RC6
RC7
RB7
Note 1:
1
2
3
4
5
6
7
8
9
10
PIC16F631/677/685/687/689/690
PIC16F639
20
19
18
17
16
15
14
13
12
11
V
SS
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RC0
RC1
RC2
RB4
RB5
RB6
PIC16F631, PIC16F677, PIC16F685, PIC16F687, PIC16F689 and PIC16F690 only.
FIGURE 1-5:
QFN
20-PIN DIAGRAM FOR PIC16F631/677/685/687/689/690
RA4/OSC2/CLKOUT
RA5/OSC1/CLKIN
19
20
18
17
RA3/MCLR/V
PP
RC5
RC4
RC3
RC6
16
15
RA0/ICSPDAT
V
DD
V
SS
1
2
3
4
5
10
6
7
8
9
RA1/ICSPCLK
RA2
RC0
RC1
RC2
14
PIC16F631/677/
685/687/689/690
13
12
11
RC7
RB7
RB5
2009-2015 Microchip Technology Inc.
RB6
RB4
DS40001204J-page 3
PIC12F6XX/16F6XX
2.0
2.1
MEMORY DESCRIPTION
Program Memory Map
2.3
Calibration Word
The user memory space extends from 0x0000 to
0x1FFF. In Program/Verify mode, the program memory
space extends from 0x0000 to 0x3FFF, with the first half
(0x0000-0x1FFF) being user program memory and the
second half (0x2000-0x3FFF) being configuration
memory. The PC will increment from 0x0000 to 0x1FFF
and wrap to 0x000, 0x2000 to 0x3FFF and wrap around
to 0x2000 (not to 0x0000). Once in configuration
memory, the highest bit of the PC stays a ‘1’, thus always
pointing to the configuration memory. The only way to
point to user program memory is to reset the part and re-
enter Program/Verify mode as described in
Section 3.0
“Program/Verify Mode”.
For the PIC12F6XX/16F6XX (not including PIC12F635/
636/639) devices, the configuration memory space,
0x2000 to 0x2008 are physically implemented. However,
only locations 0x2000 to 0x2003, 0x2007 and 0x2008 are
available. Other locations are reserved.
For the PIC12F635/636/639 devices, the configuration
memory space (0x2000-0x2009) are physically
implemented. However, only locations 0x2000 to
0x2003 and locations 0x2006 to 0x2009 are available.
Other locations are reserved.
For the PIC16F631/677/685/687/689/690 (not including
PIC12F635/636/639) devices, the 8 MHz Internal
Oscillator (INTOSC), the Power-on Reset (POR) and
the Brown-out Reset (BOR) modules are factory
calibrated. These values are stored in the Calibration
Word (0x2008). See the applicable device data sheet
for more information.
For the PIC12F635/636/639 devices, the 8 MHz
Internal Oscillator (INTOSC), the Power-on Reset and
the Brown-out Reset modules are factory calibrated
and stored in the Calibration Word (0x2008). The
Wake-up Reset (WUR) and Low-Voltage Detect (LVD)
modules are factory calibrated and stored in the
Calibration Word (0x2009). See the applicable device
data sheet for more information.
The Calibration Word locations are written at the time
of manufacturing and are not erased when a Bulk
Erase is performed. See
Section 3.1.5.10 “Bulk
Erase Program Memory”
for more information on the
various erase sequences. However, it is possible to
inadvertently write to these locations. The device may
not function properly or may operate outside of specifi-
cations if the Calibration Word locations do not contain
the correct value. Therefore, it is recommended that
the Calibration Words be read prior to any program-
ming procedure and verified after programming is com-
plete. See
Figure 3-21
for a flowchart of the
recommended verification procedure.
The device should not be used if the verification of the
Calibration Word values fail after the device is
programmed. The 0x3FFF value is a special case, it is
a valid calibration value but, it is also the erased state
of the register.
2.2
User ID Locations
A user may store identification information (user ID) in
four designated locations. The user ID locations are
mapped in 0x2000 to 0x2003. It is recommended that
the user use only the seven Least Significant bits (LSb)
of each user ID location. The user ID locations read out
normally, even after code protection is enabled. It is
recommended that ID locations are written as
‘xx
xxxx xbbb bbbb’
where ‘bbb
bbbb’
is user ID
information.
The 14 bits may be programmed, but only the seven
LSb’s are displayed by MPLAB
®
IDE. The
xxxx’s
are
“don’t care” bits and are not read by MPLAB
®
IDE.
TABLE 1:
Device
PIC12F635
PIC12F683
PIC16F631
PIC16F636
PIC16F639
PIC16F677
PIC16F684
PIC16F685
PIC16F687
PIC16F688
PIC16F689
PIC16F690
MEMORY CAPACITY
EEDATA
128 x 8
256 x 8
128 x 8
256 x 8
256 x 8
256 x 8
256 x 8
256 x 8
256 x 8
256 x 8
256 x 8
256 x 8
Program Flash
1k x 14
2k x 14
1k x 14
2k x 14
2k x 14
2k x 14
2k x 14
4k x 14
2k x 14
4k x 14
4k x 14
4k x 14
DS40001204J-page 4
2009-2015 Microchip Technology Inc.
PIC12F6XX/16F6XX
FIGURE 2-1:
PIC16F631 PROGRAM MEMORY MAPPING
1 KW
Implemented
03FF
Program Memory
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009-207F
User ID Location
User ID Location
1FFF
User ID Location
User ID Location
Reserved
Reserved
Device ID
Configuration Word
Calibration Word
Reserved
Maps to
2000-207F
Configuration Memory
2000
2080
Implemented
Maps to
0-3FF
3FFF
2009-2015 Microchip Technology Inc.
DS40001204J-page 5
