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PM6341-QI

描述:
Telecom IC, CMOS, PQCC68,
分类:
文件大小:
935KB,共272页
制造商:
概述
Telecom IC, CMOS, PQCC68,
器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
LAPIS Semiconductor Co Ltd
包装说明
QCCJ, LDCC68,1.0SQ
Reach Compliance Code
unknown
运营商类型
CEPT PCM-30/E-1
JESD-30 代码
S-PQCC-J68
JESD-609代码
e0
端子数量
68
最高工作温度
85 °C
最低工作温度
-40 °C
封装主体材料
PLASTIC/EPOXY
封装代码
QCCJ
封装等效代码
LDCC68,1.0SQ
封装形状
SQUARE
封装形式
CHIP CARRIER
电源
5 V
认证状态
Not Qualified
最大压摆率
95 mA
标称供电电压
5 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子面层
Tin/Lead (Sn/Pb)
端子形式
J BEND
端子节距
1.27 mm
端子位置
QUAD
文档预览
PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
PM6341
E1XC
E1 FRAMER/TRANSCEIVER
DATA SHEET
ISSUE 8: JUNE 1998
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
PUBLIC REVISION HISTORY
Issue
No.
8
Issue
Date
June
1998
Details of Change
Data Sheet Reformatted — No
Change in Technical Content.
Generated R8 data sheet from
PMC-901204, R10
7
6
5
4
3
2
1
Creation of Document
February
1996
June
1995
Update to rev 9 of Eng Doc
Update to rev 6 of Eng Doc
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
CONTENTS
1
2
3
4
5
6
7
8
9
FEATURES ............................................................................................... 1
APPLICATIONS ........................................................................................ 4
REFERENCES ......................................................................................... 5
APPLICATION EXAMPLES ...................................................................... 7
BLOCK DIAGRAM.................................................................................. 10
DESCRIPTION ....................................................................................... 11
PIN DIAGRAM ........................................................................................ 13
PIN DESCRIPTION ................................................................................ 15
FUNCTIONAL DESCRIPTION ............................................................... 40
9.1
9.2
1.3
1.4
DIGITAL RECEIVE INTERFACE (DRIF) ...................................... 40
ANALOG PULSE SLICER (RSLC) .............................................. 40
CLOCK AND DATA RECOVERY (CDRC) .................................... 42
FRAMER (FRMR) ........................................................................ 44
1.4.1 FRAME FIND .................................................................... 45
1.4.2 CRC FRAME FIND............................................................ 48
1.4.3 CRC CHECK AND AIS DETECTION ................................ 49
1.1.4 SIGNALLING FRAME FIND.............................................. 49
1.1.5 ALARM INTEGRATION..................................................... 50
1.5
1.6
1.7
1.8
PERFORMANCE MONITOR COUNTERS (PMON) .................... 51
HDLC RECEIVER (RFDL) ........................................................... 51
ELASTIC STORE (ELST) ............................................................ 52
SIGNALLING EXTRACTOR (SIGX)............................................. 52
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
i
PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
1.9
1.10
1.11
1.12
1.13
1.14
1.15
1.16
1.17
1.18
10
11
BACKPLANE RECEIVE INTERFACE (BRIF) .............................. 53
TRANSMITTER (TRAN) .............................................................. 53
TRANSMIT PER-CHANNEL SERIAL CONTROLLER (TPSC) .... 54
HDLC TRANSMITTER (XFDL) .................................................... 54
DIGITAL JITTER ATTENUATOR (DJAT)....................................... 55
TIMING OPTIONS (TOPS) .......................................................... 59
DIGITAL DS-1 TRANSMIT INTERFACE (DTIF) ........................... 60
ANALOG PULSE GENERATOR (XPLS)...................................... 60
BACKPLANE TRANSMIT INTERFACE (BTIF) ............................ 62
MICROPROCESSOR INTERFACE (MPIF) ................................. 62
REGISTER DESCRIPTION.................................................................... 63
NORMAL MODE REGISTER DESCRIPTION........................................ 66
11.1
INTERNAL REGISTERS ............................................................. 67
1.1.1 REGISTERS 49-4FH: LATCHING PERFORMANCE DATA
........................................................................................ 177
12
TEST FEATURES DESCRIPTION ....................................................... 187
12.1
12.2
INTERNAL REGISTERS ........................................................... 190
TEST MODE 0 ........................................................................... 191
13
14
TIMING DIAGRAMS ............................................................................. 193
OPERATIONS....................................................................................... 198
14.1
14.2
14.3
CONFIGURING THE E1XC FROM RESET............................... 198
USING THE INTERNAL FDL TRANSMITTER ........................... 199
USING THE INTERNAL FDL RECEIVER.................................. 201
14.3.1 KEY USED ON SUBSEQUENT DIAGRAMS: ................. 205
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
ii
PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
14.4
USING THE LOOPBACK MODES............................................. 208
14.4.1 PAYLOAD LOOPBACK ................................................... 209
14.4.2 LINE LOOPBACK............................................................ 209
14.4.3 DIAGNOSTIC DIGITAL LOOPBACK ............................... 210
14.4.4 DIAGNOSTIC METALLIC LOOPBACK ........................... 211
14.5
USING THE PER-CHANNEL SERIAL CONTROLLERS ........... 212
14.5.1 INITIALIZATION .............................................................. 212
14.5.2 DIRECT ACCESS MODE ............................................... 212
14.5.3 INDIRECT ACCESS MODE ............................................ 213
14.6
1.7
1.8
1.9
1.10
INTERFACING TO THE ANALOG PULSE SLICER ................... 213
ALTERNATIVE LONGITUDINALLY BALANCED RECEIVE
INTERFACE ............................................................................... 218
PROGRAMMING THE XPLS WAVEFORM TEMPLATE ............ 221
CODE REGISTER PROGRAMMING SEQUENCE FOR CUSTOM
WAVEFORMS ............................................................................ 224
USING THE DIGITAL JITTER ATTENUATOR............................ 224
1.10.1 DEFAULT APPLICATION................................................. 224
1.10.2 DATA BURST APPLICATION .......................................... 225
1.10.3 ELASTIC STORE APPLICATION.................................... 225
1.10.4 ALTERNATE TCLKO REFERENCE APPLICATION ........ 226
1.10.5 CHANGING THE JITTER TRANSFER FUNCTION ........ 226
1.11
2
3
USING THE PERFORMANCE MONITOR COUNTER VALUES 226
ABSOLUTE MAXIMUM RATINGS........................................................ 230
CAPACITANCE ..................................................................................... 231
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
iii
参数对比
与PM6341-QI相近的元器件有:PM6341-RI。描述及对比如下:
型号 PM6341-QI PM6341-RI
描述 Telecom IC, CMOS, PQCC68, Telecom IC, CMOS, PQFP80,
是否Rohs认证 不符合 不符合
厂商名称 LAPIS Semiconductor Co Ltd LAPIS Semiconductor Co Ltd
包装说明 QCCJ, LDCC68,1.0SQ QFP, QFP80,.7SQ
Reach Compliance Code unknown unknown
运营商类型 CEPT PCM-30/E-1 CEPT PCM-30/E-1
JESD-30 代码 S-PQCC-J68 S-PQFP-G80
JESD-609代码 e0 e0
端子数量 68 80
最高工作温度 85 °C 85 °C
最低工作温度 -40 °C -40 °C
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 QCCJ QFP
封装等效代码 LDCC68,1.0SQ QFP80,.7SQ
封装形状 SQUARE SQUARE
封装形式 CHIP CARRIER FLATPACK
电源 5 V 5 V
认证状态 Not Qualified Not Qualified
最大压摆率 95 mA 95 mA
标称供电电压 5 V 5 V
表面贴装 YES YES
技术 CMOS CMOS
温度等级 INDUSTRIAL INDUSTRIAL
端子面层 Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
端子形式 J BEND GULL WING
端子节距 1.27 mm 0.635 mm
端子位置 QUAD QUAD
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