INTEGRATED CIRCUITS
PZ3128A/PZ3128D
128 macrocell CPLD with enhanced
clocking
Preliminary specification
Supersedes data of 1999 May 07
IC27 Data Handbook
1999 Jun 29
Philips
Semiconductors
Philips Semiconductors
Product specification
128 macrocell CPLD with enhanced clocking
PZ3128A/PZ3128D
FEATURES
•
Industry’s first TotalCMOS™ PLD – both CMOS design and
•
Fast Zero Power (FZP™) design technique provides ultra-low
•
3 Volt, In-System Programmable (ISP) using a JTAG interface
–
–
–
–
–
On-chip supervoltage generation
ISP commands include: Enable, Erase, Program, Verify
Supported by multiple ISP programming platforms
4 pin JTAG interface (TCK, TMS, TDI, TDO)
JTAG commands include: Bypass, Idcode
power and very high speed
process technologies
DESCRIPTION
The PZ3128A/PZ3128D CPLD (Complex Programmable Logic
Device) is a member of the Fast Zero Power (FZP™) family of
CPLDs from Philips Semiconductors. These devices combine high
speed and zero power in a 128 macrocell CPLD. With the FZP™
design technique, the PZ3128A/PZ3128D offers true pin-to-pin
speeds of 7.5ns, while simultaneously delivering power that is less
than 100µA at standby without the need for ‘turbo bits’ or other
power down schemes. By replacing conventional sense amplifier
methods for implementing product terms (a technique that has been
used in PLDs since the bipolar era) with a cascaded chain of pure
CMOS gates, the dynamic power is also substantially lower than
any competing CPLD – 70% lower at 50MHz. These devices are the
first TotalCMOS™ PLDs, as they use both a CMOS process
technology
and
the patented full CMOS FZP™ design technique.
The Philips FZP™ CPLDs introduce the new patented XPLA™
(eXtended Programmable Logic Array) architecture. The XPLA™
architecture combines the best features of both PLA and PAL™ type
structures to deliver high speed and flexible logic allocation that
results in superior ability to make design changes with fixed pinouts.
The XPLA™ structure in each logic block provides a fast 7.5ns
PAL™ path with 5 dedicated product terms per output. This PAL™
path is joined by an additional PLA structure that deploys a pool of
32 product terms to a fully programmable OR array that can allocate
the PLA product terms to any output in the logic block. This
combination allows logic to be allocated efficiently throughout the
logic block and supports as many as 37 product terms on an output.
The speed with which logic is allocated from the PLA array to an
output is only 1.5ns, regardless of the number of PLA product terms
used, which results in worst case t
PD
’s of only 9ns from any pin to
any other pin. In addition, logic that is common to multiple outputs
can be placed on a single PLA product term and shared across
multiple outputs via the OR array, effectively increasing design
density.
The PZ3128A/PZ3128D CPLDs are supported by industry standard
CAE tools (Cadence, Exemplar Logic, Mentor, OrCAD, Synopsys,
Synario, Viewlogic, MINC), using text (Abel, VHDL, Verilog) and/or
schematic entry. Design verification uses industry standard
simulators for functional and timing simulation. Development is
supported on personal computer, Sparc, and HP platforms. Device
fitting uses either MINC or Philips Semiconductors-developed tools.
The PZ3128A/PZ3128D CPLD is electrically reprogrammable using
industry standard device programmers from vendors such as Data
I/O, BP Microsystems, SMS, and others. The PZ3128A/PZ3128D
also includes an industry-standard, IEEE 1149.1, JTAG interface
through which In-System Programming (ISP) and reprogramming of
the device are supported.
•
High speed pin-to-pin delays of 7.5ns
•
Ultra-low static power of less than 100µA
•
Dynamic power that is 70% lower at 50MHz than competing
•
5V tolerant I/Os to support mixed voltage systems
•
100% routable with 100% utilization while all pins and all
•
Deterministic timing model that is extremely simple to use
•
Up to 20 clocks available
•
Support for complex asynchronous clocking
•
Innovative XPLA™ architecture combines high speed with
•
1000 erase/program cycles guaranteed
•
20 years data retention guaranteed
•
Logic expandable to 37 product terms
•
Advanced 0.35µ E
2
CMOS process
•
Security bit prevents unauthorized access
•
Design entry and verification using industry standard and Philips
•
Reprogrammable using industry standard device programmers
•
Innovative Control Term structure provides either sum terms or
product terms in each logic block for:
–
Programmable 3-State buffer
–
Asynchronous macrocell register preset/reset
–
up to 2 asynchronous clocks
CAE tools
extreme flexibility
macrocells are fixed
devices
•
Programmable global 3-State pin facilitates ‘bed of nails’ testing
•
Available in TQFP and LQFP packages
•
Available in both Commercial and Industrial grades
•
Industrial grade operates from 2.7 to 3.6 Volts
Table 1. PZ3128A/PZ3128D Features
PZ3128A/PZ3128D
Usable gates
Maximum inputs
Maximum I/Os
Number of macrocells
Propagation delay (ns)
Packages
4000
100
96
128
7.5
100-pin TQFP, 128-pin LQFP
without using logic resources
PAL is a registered trademark of Advanced Micro Devices, Inc.
1999 Jun 29
2
853–2163 21884
Philips Semiconductors
Product specification
128 macrocell CPLD with enhanced clocking
PZ3128A/PZ3128D
ORDERING INFORMATION
ORDER CODE
PZ3128AS7BP
PZ3128AS10BP
PZ3128AS12BP
PZ3128AS7BE
PZ3128AS10BE
PZ3128AS12BE
PZ3128DS10BP
PZ3128DS15BP
PZ3128DS10BE
PZ3128DS15BE
DESCRIPTION
100-pin TQFP, 7.5ns t
PD
, Commercial temperature range, 3.0 to 3.6 volt power supply
100-pin TQFP, 10ns t
PD
, Commercial temperature range, 3.0 to 3.6 volt power supply
100-pin TQFP, 12ns t
PD
, Commercial temperature range, 3.0 to 3.6 volt power supply
128-pin LQFP, 7.5ns t
PD
, Commercial temperature range, 3.0 to 3.6 volt power supply
128-pin LQFP, 10ns t
PD
, Commercial temperature range, 3.0 to 3.6 volt power supply
128-pin LQFP, 12ns t
PD
, Commercial temperature range, 3.0 to 3.6 volt power supply
100-pin TQFP, 10ns t
PD
, Industrial temperature range, 2.7 to 3.6 volt power supply
100-pin TQFP, 15ns t
PD
, Industrial temperature range, 2.7 to 3.6 volt power supply
128-pin LQFP, 10ns t
PD
, Industrial temperature range, 2.7 to 3.6 volt power supply
128-pin LQFP, 15ns t
PD
, Industrial temperature range, 2.7 to 3.6 volt power supply
I/O
COUNT
80
80
80
96
96
96
80
80
96
96
DRAWING
NUMBER
SOT386-1
SOT386-1
SOT386-1
SOT425-1
SOT425-1
SOT425-1
SOT386-1
SOT386-1
SOT425-1
SOT425-1
XPLA™ ARCHITECTURE
Figure 1 shows a high level block diagram of a 128 macrocell device
implementing the XPLA™ architecture. The XPLA™ architecture
consists of logic blocks that are interconnected by a Zero-power
Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each
logic block is essentially a 36V16 device with 36 inputs from the ZIA
and 16 macrocells. Each logic block also provides 32 ZIA feedback
paths from the macrocells and I/O pins.
From this point of view, this architecture looks like many other CPLD
architectures. What makes the CoolRunner™ family unique is what
is inside each logic block and the design technique used to
implement these logic blocks. The contents of the logic block will be
described next.
MC0
MC1
I/O
MC15
16
16
16
16
LOGIC
BLOCK
36
36
LOGIC
BLOCK
MC0
MC1
I/O
MC15
MC0
MC1
I/O
MC15
16
16
ZIA
LOGIC
BLOCK
36
36
LOGIC
BLOCK
16
16
LOGIC
BLOCK
36
36
LOGIC
BLOCK
MC0
MC1
I/O
MC15
MC0
MC1
I/O
MC15
16
16
MC0
MC1
I/O
MC15
16
16
MC0
MC1
I/O
MC15
16
16
16
16
LOGIC
BLOCK
36
36
LOGIC
BLOCK
MC0
MC1
I/O
MC15
SP00464
Figure 1. Philips XPLA CPLD Architecture
1999 Jun 29
3
Philips Semiconductors
Product specification
128 macrocell CPLD with enhanced clocking
PZ3128A/PZ3128D
Logic Block Architecture
Figure 2 illustrates the logic block architecture. Each logic block
contains control terms, a PAL array, a PLA array, and 16 macrocells.
The 6 control terms can individually be configured as either SUM or
PRODUCT terms, and are used to control the preset/reset and
output enables of the 16 macrocells’ flip-flops. In addition, two of the
control terms can be used as clock signals (see Macrocell
Architecture section for details). The PAL array consists of a
programmable AND array with a fixed OR array, while the PLA array
consists of a programmable AND array with a programmable OR
array. The PAL array provides a high speed path through the array,
while the PLA array provides increased product term density.
Each macrocell has 5 dedicated product terms from the PAL array.
The pin-to-pin t
PD
of the PZ3128A/PZ3128D device through the PAL
array is 7.5ns. If a macrocell needs more than 5 product terms, it
simply gets the additional product terms from the PLA array. The
PLA array consists of 32 product terms, which are available for use
by all 16 macrocells. The additional propagation delay incurred by a
macrocell using 1 or all 32 PLA product terms is just 1.5ns. So the
total pin-to-pin t
PD
for the PZ3128A/PZ3128D using 6 to 37 product
terms is 9ns (7.5ns for the PAL + 1.5ns for the PLA).
36 ZIA INPUTS
CONTROL
5
6
PAL
ARRAY
PLA
ARRAY
(32)
SP00435A
Figure 2. Philips XPLA Logic Block Architecture
1999 Jun 29
4
TO 16 MACROCELLS
Philips Semiconductors
Product specification
128 macrocell CPLD with enhanced clocking
PZ3128A/PZ3128D
Macrocell Architecture
Figure 3 shows the architecture of the macrocell used in the
CoolRunner™ PZ3128A/PZ3128D. The macrocell can be configured
as either a D or T type flip-flop or a combinatorial logic function. A
D-type flip-flop is generally more useful for implementing state
machines and data buffering while a T-type flip-flop is generally
more useful in implementing counters. Each of these flip-flops can
be clocked from any one of six sources. Four of the clock sources
(CLK0, CLK1, CLK2, CLK3) are connected to low-skew, device-wide
clock networks designed to preserve the integrity of the clock signal
by reducing skew between rising and falling edges. Clock 0 (CLK0)
is designated as a “synchronous” clock and must be driven by an
external source. Clock 1 (CLK1), Clock 2 (CLK2), and Clock 3
(CLK3) can be used as “synchronous” clocks that are driven by an
external source, or as “asynchronous” clocks that are driven by a
macrocell equation. CLK0, CLK1, CLK2 and CLK3 can clock the
macrocell flip-flops on either the rising edge or the falling edge of the
clock signal. The other clock sources are two of the six control terms
(CT2 and CT3) provided in each logic block. These clocks can be
individually configured as either a PRODUCT term or SUM term
equation created from the 36 signals available inside the logic block.
The timing for asynchronous and control term clocks is different in
that the t
CO
time is extended by the amount of time that it takes for
the signal to propagate through the array and reach the clock
network, and the t
SU
time is reduced. Please see the app note titled
“Understanding CoolRunner
™
Clocking Options”
for more detail.
The six control terms of each logic block are used to control the
asynchronous Preset/Reset of the flip-flops and the enable/disable
of the output buffers in each macrocell. Control terms CT0 and CT1
are used to control the asynchronous Preset/Reset of the
macrocell’s flip-flop. Note that the Power-on Reset leaves all
macrocells in the “zero” state when power is properly applied, and
that the Preset/Reset feature for each macrocell can also be
disabled. Control terms CT2 and CT3 can be used as a clock signal
to the flip-flops of the macrocells, and as the Output Enable of the
macrocell’s output buffer. Control terms CT4 and CT5 can be used
to control the Output Enable of the macrocell’s output buffer. Having
four dedicated Output Enable control terms ensures that the
CoolRunner™ devices are PCI compliant. The output buffers can
also be always enabled or always disabled. All CoolRunner™
devices also provide a Global Tri-State (GTS) pin, which, when
enabled and pulled Low, will 3-State all the outputs of the device.
This pin is provided to support “In-Circuit Testing” or “Bed-of-Nails
Testing”.
There are two feedback paths to the ZIA: one from the macrocell,
and one from the I/O pin. The ZIA feedback path before the output
buffer is the macrocell feedback path, while the ZIA feedback path
after the output buffer is the I/O pin feedback path. When the
macrocell is used as an output, the output buffer is enabled, and the
macrocell feedback path can be used to feedback the logic
implemented in the macrocell. When the I/O pin is used as an input,
the output buffer will be 3-Stated and the input signal will be fed into
the ZIA via the I/O feedback path, and the logic implemented in the
buried macrocell can be fed back to the ZIA via the macrocell
feedback path. It should be noted that unused inputs or I/Os should
be properly terminated (see the section on Terminations in this data
sheet and the Application Note
Terminating Unused CoolRunner
™
I/O Pins).
TO ZIA
PAL
PLA
D/T
INIT
(P or R)
CT0
CT1
GND
Q
CLK0
CLK0
CLK1
CLK1
CLK2
CLK2
CLK3
CLK3
GTS
GND
CT4
CT5
V CC
GND
CT2
CT3
SP00558
Figure 3. PZ3128A/PZ3128D Macrocell Architecture
1999 Jun 29
5
