R1QBA36**CB* / R1QEA36**CB* Series
R1QBA3636CBG / R1QBA3618CBG
/ R1QBA3609CBG
R1QEA3636CBG / R1QEA3618CBG
/ R1QEA3609CBG
R1QHA3636CBG / R1QHA3618CBG / R1QHA3609CBG
R1QLA3636CBG / R1QLA3618CBG / R1QLA3609CBG
36-Mbit DDRII+ SRAM
2-word Burst
Description
The R1Q#A3636 is a 1,048,576-word by 36-bit and the R1Q#A3618 is a 2,097,152-word by 18-bit synchronous
double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor
memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are
controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products
are suitable for applications which require synchronous operation, high speed, low voltage, high density and
wide bit configuration. These products are packaged in 165-pin plastic FBGA package.
#
= B: Latency =2.5, w/o ODT
#
= E: Latency =2.5, w/ ODT
# = H: Latency =2.0, w/o ODT
# = L: Latency =2.0, w/ ODT
R10DS0159EJ0009
Rev. 0.09a
2011.09.14
Features
Power Supply
• 1.8 V for core (V
DD
), 1.4 V to V
DD
for I/O (V
DDQ
)
Clock
• Fast clock cycle time for high bandwidth
• Two input clocks (K and /K) for precise DDR timing at clock rising edges only
• Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems
• Clock-stop capability with s restart
I/O
• Common data input/output bus
• Pipelined double data rate operation
• HSTL I/O
• User programmable output impedance
• DLL/PLL circuitry for wide output data valid window and future frequency scaling
• Data valid pin (QVLD) to indicate valid data on the output
Function
• Two-tick burst for low DDR transaction size
• Internally self-timed write control
• Simple control logic for easy depth expansion
• JTAG 1149.1 compatible test access port
Package
• 165 FBGA package (15 x 17 x 1.4 mm)
Notes:
1.
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress
Semiconductor, IDT, Samsung, and Renesas Electronics Corp. (QDR Co-Development Team)
2. The specifications of this device are subject to change without notice. Please contact your nearest
Renesas Electronics Sales Office regarding specifications.
3. Refer to
"http://www.renesas.com/products/memory/fast_sram/qdr_sram/qdr_sram_root.jsp"
for the latest and detailed information.
4. Descriptions about x9 parts in this datasheet are just for reference.
Rev. 0.09a : 2011.09.14
R10DS0159EJ0009
PAGE : 1
Common
R1QBA36**CB* / R1QEA36**CB* Series
Part Number Definition
Part Number Definition Table
No.
Example
0
1
2
3
4
5
6
4
7
3
8
9 10 11 - 12 13 14 15 16
-
2
0 R B 0
R 1 Q A A 4
6 R B G
Rev. 0.09a : 2011.09.14
R10DS0159EJ0009
PAGE : 2
hinS=
00000.0000.0000.0000.0000
--
-
11111.1111
.1111.1111.1111
---
00000.0000.0000.0000.0000---
036M
R1QBA36**CB* / R1QEA36**CB* Series
36M QDR II+ / DDR II+ SRAM Lineup
- Renesas supports or plans to support the parts listed below.
QDR II+ / DDR II+
Frequency (max)
(MHz)
Cycle Time (min)
(ns)
yy
Part Number
R1Q A A36 18 C Bv-
yy
R1Q A A36 36 C Bv-
yy
R1Q B A36 18 C Bv-
yy
R1Q B A36 36 C Bv-
yy
R1Q C A36 18 C Bv-
yy
R1Q C A36 36 C Bv-
yy
R1Q D A36 18 C Bv-
yy
R1Q D A36 36 C Bv-
yy
R1Q E A36 18 C Bv-
yy
R1Q E A36 36 C Bv-
yy
R1Q F A36 18 C Bv-
yy
R1Q F A36 36 C Bv-
yy
R1Q G A36 18 C Bv-
yy
R1Q G A36 36 C Bv-
yy
R1Q H A36 18 C Bv-
yy
R1Q H A36 36 C Bv-
yy
R1Q J A36 18 C Bv-
yy
R1Q J A36 36 C Bv-
yy
R1Q K A36 18 C Bv-
yy
R1Q K A36 36 C Bv-
yy
R1Q L A36 18 C Bv-
yy
R1Q L A36 36 C Bv-
yy
R1Q M A36 18 C Bv-
yy
R1Q M A36 36 C Bv-
yy
Product
Type
Burst
Length
Latency
(Cycle)
ODT
Organi-
zation
533
500
450
2.22
-22
-22
-22
-22
-22
-22
-22
-25
-25
-25
-25
-25
-25
400
2.50
-25
375
2.66
-27
333
3.00
-30
333
3.00
-30
QDR II / DDR II
300
3.30
-33
250
4.00
-40
200
5.00
-50
No
1.875 2.00
-19
-19
-19
-19
-19
-19
-19
-20
-20
-20
-20
-20
-20
-20
17
18
20
21
23
24
26
27
29
30
32
33
35
36
38
39
41
42
44
45
47
48
50
51
QDRII+ B4
2.5
B2
DDRII+
B4
QDRII+ B4
B2
DDRII+
B4
QDRII+ B4
2.0
B2
DDRII+
B4
QDRII+ B4
B2
DDRII+
B4
Yes
2.0
No
Yes
2.5
No
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
x18
x36
Notes:
1. "yy" represents the
speed bin.
"R1QAA3636CBG-20" can operate at
500 MHz(max)
of frequency, for example.
2. "v" represents the
package size.
If "v" = "G" then size is 15 x 17 mm, and if "v" = "A" then 13 x 15 mm.
3. The part which is not listed above is not supported, as of the day when this datasheet was issued,
in spite of the existence of the part number or datasheet.
Rev. 0.09a : 2011.09.14
R10DS0159EJ0009
PAGE : 3
R1QBA36**CB* / R1QEA36**CB* Series
Pin Arrangement
R1Q4A3636
(Top) /
R1QB(H)A3636
(Mid) /
R1QE(L)A3636
(Bottom)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
/CQ
NC
NC
NC
NC
NC
NC
/DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC
3
SA
4
R-/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
/BW2
/BW3
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
6
/K
K
SA0
NC
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
7
/BW1
/BW0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
Top
Mid
Bottom
8
/LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
NC
NC
DQ17
NC
DQ15
NC
NC
V
REF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
DQ27 DQ18
NC
DQ28
DQ29 DQ19
NC
DQ20
DQ30 DQ21
DQ31 DQ22
V
REF
NC
NC
NC
V
DDQ
DQ32
DQ23
DQ34
DQ33 DQ24
DQ35 DQ25
NC
TCK
DQ26
SA
SA
C
QVLD
SA
QVLD
/C
NC
SA
ODT
(Top View)
R1Q4A3636
R1QB(H)A3636
R1QE(L)A3636
Notes: 1. Address expansion order for future higher density SRAMs: 10A
2. NC pins can be left floating or connected to 0V
V
DDQ
.
2A
7A
5B.
R1Q4A3618
(Top) /
R1QB(H)A3618
(Mid) /
R1QE(L)A3618
(Bottom)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
/CQ
NC
NC
NC
NC
NC
NC
/DOFF
NC
NC
NC
NC
NC
2
NC
DQ9
NC
NC
NC
DQ12
NC
V
REF
NC
NC
DQ15
NC
NC
3
SA
NC
NC
DQ10
DQ11
NC
DQ13
V
DDQ
NC
DQ14
NC
NC
DQ16
4
R-/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
5
/BW1
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
6
/K
K
SA0
NC
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
7
NC
/BW0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
8
/LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
10
SA
NC
DQ7
NC
NC
NC
NC
V
REF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
SA
SA
NC
V
SS
C
QVLD
SA
DQ17
SA
SA
NC
NC
SA
NC
P
QVLD
/C
NC
SA
R
SA
SA
TDO TCK
SA
SA
SA
ODT
(Top View)
Notes: 1. Address expansion order for future higher density SRAMs: 10A 2A
2. NC pins can be left floating or connected to 0V
V
DDQ
.
7A
5B.
Rev. 0.09a : 2011.09.14
R10DS0159EJ0009
PAGE : 4
R1QBA36**CB* / R1QEA36**CB* Series
Pin Arrangement
R1Q4A3609
(Top) /
R1QB(H)A3609
(Mid) /
R1QE(L)A3609
(Bottom)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
/CQ
NC
NC
NC
NC
NC
NC
/DOFF
NC
NC
NC
NC
NC
2
NC
NC
NC
NC
NC
NC
NC
V
REF
NC
NC
DQ7
NC
NC
3
SA
NC
NC
NC
DQ5
NC
DQ6
V
DDQ
NC
NC
NC
NC
NC
4
R-/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
5
NC
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
6
/K
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
7
NC
/BW
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
8
/LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
Just Reference
10
SA
NC
NC
NC
NC
NC
NC
V
REF
DQ2
NC
NC
NC
11
CQ
DQ4
NC
NC
DQ3
NC
NC
ZQ
NC
NC
DQ1
NC
SA
NC
SA
NC
NC
V
SS
C
QVLD
NC
NC
NC
SA
NC
SA
SA
DQ8
SA
P
DQ0
QVLD
/C
NC
TMS
TDO TCK
SA
SA
SA
SA
SA
SA
R
TDI
ODT
(Top View)
Notes: 1. Address expansion order for future higher density SRAMs: 10A 2A 7A 5B.
2. NC pins can be left floating or connected to 0V
V
DDQ
.
3. Note that 6C is not SA0 and 7C is not SA1 in x9 product. Thus 9 product does not
permit random start address on the two least significant address bits. SA0, SA1 = 0
at the start of each address.
Rev. 0.09a : 2011.09.14
R10DS0159EJ0009
PAGE : 5
