128Mb: x4, x8, x16
DDR SDRAM
DOUBLE DATA RATE
(DDR) SDRAM
•
PC1600 and PC2100 compatible
•
VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
•
Bi-directional data strobe (DQS) transmitted/ received with
data, i.e., source-synchronous data capture (x16 has two –
one per byte)
•
Internal, pipelined double-data-rate (DDR) architecture;
two data accesses per clock cycle
•
Differential clock inputs (CK and CK#)
•
Commands entered on each positive CK edge
•
DQS edge-aligned with data for READs; center-aligned
with data for WRITEs
•
DLL to align DQ and DQS transitions with CK
•
Four internal banks for concurrent operation
•
Data mask (DM) for masking write data (x16 has two –
one per byte)
•
Programmable burst lengths: 2, 4, or 8
•
Auto precharge option
•
Auto Refresh
•
Longer lead TSOP for improved reliability (OCPL)
•
2.5V I/O (SSTL_2 compatible)
Timing – Cycle Time
7.5ns @ CL = 2.5 (PC2100)
10ns @ CL = 2.5 (PC1600)
Part number example:
(For part numbers prior to December
2004, refer to
page 13
for decoding.)
-75A
-8A
SAA16M8T95AV4TL-75A
Options:
Family
SpecTek Memory
Configuration
32 Meg x 4 (8 Meg x 4 x 4 banks)
16 Meg x 8 (4 Meg x 8 x 4 banks)
8 Meg x 16 (2 Meg x 16 x 4 banks)
Design ID
DDR 128 Megabit Design
(Call SpecTek Sales for details on
availability of “x” placeholders)
Voltage and refresh
2.5V, Auto Refresh
2.5V, Self or Auto Refresh
Plastic Package – OCPL
66-pin TSOP
(400 mil width, 0.65mm pin pitch)
Designation:
SAA
32M4
16M8
8M16
Yx6x
V4
R4
TL
PDF: 09005aef80505d1b / Source: 09005aef80469e44
128Mb: x4, x8, x16 DDR SDRAM
Rev: 11/23/2004
1
www.spectek.com
SpecTek reserves the right to change products or specifications
without notice.
©
2001, 2002, 2004 SpecTek
128Mb: x4, x8, x16
DDR SDRAM
GENERAL DESCRIPTION
The 128Mb DDR SDRAM is a high-speed CMOS,
dynamic random-access memory containing 134,217,728 bits.
It is internally configured as a quad-bank DRAM.
The 128Mb DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The double data
rate architecture is essentially a 2n-prefetch architecture with
an interface designed to transfer two data words per clock
cycle at the I/O pins. A single read or write access for the
128Mb DDR SDRAM effectively consists of a single 2n-bit
wide, one-clock-cycle data transfer at the internal DRAM core
and two corresponding
n-bit
wide, one-half-clock-cycle data
transfers at the I/O pins.
A bi-directional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at the
receiver. DQS is a strobe transmitted by the DDR SDRAM
during READs and by the memory controller during WRITEs.
DQS is edge-aligned with data for READs and center-aligned
with data for WRITEs. The x16 offering has two data strobes,
one for the lower byte and one for the upper byte.
The 128Mb DDR SDRAM operates from a differential
clock (CK and CK#); the crossing of CK going HIGH and
CK# going LOW will be referred to as the positive edge of
CK. Commands (address and control signals) are registered at
every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE
command, which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be
accessed. The address bits registered coincident with the
READ or WRITE command are used to select the bank and
the starting column location for the burst access.
The DDR SDRAM provides for programmable READ or
WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access.
As with standard SDR SDRAMs, the pipelined,
multibank architecture of DDR SDRAMs allows for
concurrent operation, thereby providing high effective
bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided, along with a power-
saving power-down mode. All inputs are compatible with the
JEDEC Standard for SSTL_2. All full drive strength outputs
are SSTL_2, Class II compatible.
NOTE 1:
The functionality and the timing specifications discussed
in this data sheet are for the DLL-enabled mode of
operation.
NOTE 2:
Throughout the data sheet, the various figures and text
refer to DQs as “DQ.” The DQ term is to be interpreted as
any and all DQ collectively, unless specifically stated
otherwise.
Additionally, the x16 is divided in to two bytes — the
lower byte and upper byte. For the lower byte (DQ0
through DQ7) DM refers to LDM and DQS refers to
LDQS; and for the upper byte (DQ8 through DQ15) DM
refers to UDM and DQS refers to UDQS.
___________________________________________________
ABSOLUTE MAXIMUM RATINGS*
V
DD
Supply Voltage
Relative to V
SS
.....................................-1V to +3.6V
V
DD
Q Supply
Voltage Relative to V
SS
......................... -1V to +3.6V
V
REF
and Inputs Voltage
Relative to V
SS
.....................................-1V to +3.6V
I/O Pins Voltage
Relative to V
SS
..........................-0.5V to V
DD
Q +0.5V
Operating Temperature, T
A
(ambient) .....…. 25°C to +70°C
Storage Temperature (plastic) ....….......... -55°C to +150°C
Power Dissipation ..................................................1W
Short Circuit Output Current .............................…..50mA
Disclaimer:
Except as specifically provided in this document,
SpecTek makes no warranties, expressed or implied,
including, but not limited to, any implied warranties of
merchantability or fitness for a particular purpose.
Any claim against SpecTek must be made within 1
year from the date of shipment from SpecTek, and
SpecTek has no liability thereafter. Any liability is limited
to replacement of the defective items or return of
amounts paid for defective items (at buyer’s election). In
no event will SpecTek be responsible for special,
indirect, consequential or incidental damages, even if
SpecTek has been advised for the possibility of such
damages. SpecTek’s liability from any cause pursuant
to this specification shall be limited to general monetary
damages in an amount not to exceed the total purchase
price of the products covered by this specification,
regardless of the form in which legal or equitable action
may be brought against SpecTek.
PDF: 09005aef80505d1b / Source: 09005aef80469e44
128Mb: x4, x8, x16 DDR SDRAM
Rev: 11/23/2004
2
www.spectek.com
SpecTek reserves the right to change products or specifications
without notice.
©
2001, 2002, 2004 SpecTek
128Mb: x4, x8, x16
DDR SDRAM
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(25°C < T
A
< +70°C; V
DD
= +2.5V ±0.2V, V
DD
Q = +2.5V ±0.2V)
PARAMETER/CONDITION
Supply Voltage
I/O Supply Voltage
I/O Reference Voltage
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Clock Input Voltage Level; CK and CK#
Clock Input Differential Voltage; CK and CK#
Clock Input Crossing Point Voltage; CK and CK#
INPUT LEAKAGE CURRENT
Any input,
0V < V
IN
< V
DD
, V
REF
pin 0V < VIN < 1.35V
(All other pins not under test = 0V)
OUTPUT LEAKAGE CURRENT
(DQs are disabled;
0V < V
OUT
< V
DD
Q)
OUTPUT LEVELS:
Full drive option - x4 , x8, x16
High Current (V
OUT
= V
DD
Q-0.373V, minimum V
REF
, minimum
V
TT
)
Low Current (V
OUT
= 0.373V, maximum V
REF
,maximum V
TT
)
OUTPUT LEVELS: Reduced drive option - x16 only
High Current (V
OUT
= V
DD
Q-0.763V, minimum V
REF
, minimum
V
TT
)
Low Current (V
OUT
= 0.763V, maximum V
REF
,maximum V
TT
)
SYMBOL
V
DD
V
DD
Q
MIN
2.3
2.3
0.49 X V
DDQ
V
REF
– 0.04
V
REF
+ 0.15
-0.3
-0.3
0.36
1.15
-2
MAX
2.7
2.7
0.51 X V
DDQ
V
REF
– 0.04
V
DD
+ 0.3
V
REF
– 0.15
V
DDQ
+ 0.3
V
DDQ
+ 0.6
1.35
2
UNITS
V
V
V
V
V
V
V
V
V
μA
NOTES
41
41, 44
6, 44
7, 44
28
28
8
9
V
REF
V
TT
V
IH
(DC)
V
IL
(DC)
V
IN
V
ID
V
IX
I
I
I
OZ
I
OH
I
OL
-7
-16.8
16.8
7
--
--
μA
mA
mA
37, 39
I
OHR
I
OLR
-9
9
--
--
mA
mA
38, 39
PDF: 09005aef80505d1b / Source: 09005aef80469e44
128Mb: x4, x8, x16 DDR SDRAM
Rev: 11/23/2004
3
www.spectek.com
SpecTek reserves the right to change products or specifications
without notice.
©
2001, 2002, 2004 SpecTek
128Mb: x4, x8, x16
DDR SDRAM
AC INPUT OPERATING CONDITIONS
(25°C < T
A
< + 70°C; V
DD
= +2.5V ±0.2V, V
DD
Q = +2.5V ±0.2V)
PARAMETER/CONDITION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Clock Input Differential Voltage; CK and CK#
Clock Input Crossing Point Voltage; CK and CK#
I/O Reference Voltage
SYMBOL
V
IH
(
AC
)
V
IL
(
AC
)
V
ID
(
AC
)
V
IX
(
AC
)
V
REF
(
AC
)
MIN
V
REF
+ 0.310
--
0.7
0.5 X V
DDQ
– 0.2
0.49 X V
DDQ
MAX
--
V
REF
– 0.310
V
DDQ
+ 0.6
0.5 X V
DDQ
+ 0.2
0.51 X V
DDQ
UNIT
S
V
V
V
V
V
NOTES
14, 28,
40
14, 28,
40
8
9
6
PDF: 09005aef80505d1b / Source: 09005aef80469e44
128Mb: x4, x8, x16 DDR SDRAM
Rev: 11/23/2004
4
www.spectek.com
SpecTek reserves the right to change products or specifications
without notice.
©
2001, 2002, 2004 SpecTek
128Mb: x4, x8, x16
DDR SDRAM
CAPACITANCE (x4, x8)
(25°C < T
A
< +70°C; V
DD
Q = +2.5V ±0.2V, V
DD
= +2.5V ±0.2V)
PARAMETER
Delta Input/Output Capacitance: DQs, DQS, DM
Delta Input Capacitance: Command and Address
Delta Input Capacitance: CK, CK#
Delta Input Capacitance: DQs, DQS, DM
Input Capacitance: Command and Address
Input Capacitance: CK, CK#
Input Capacitance: CKE
SYMBOL
DC
IO
DC
I
1
DC
I
2
C
IO
C
I
1
C
I
2
C
I
3
MIN
--
--
--
4.0
2.0
2.0
2.0
MAX
0.50
0.50
0.25
5.0
3.0
3.0
3.0
UNITS
pF
pF
pF
pF
pF
pF
pF
NOTES
24
29
29
I
DD
SPECIFICATIONS AND CONDITIONS (x4, x8)
(25°C < T
A
< +70°C; V
DD
Q = +2.5V ±0.2V, V
DD
= +2.5V ±0.2V)
PARAMETER/CONDITION
OPERATING CURRENT: One bank; Active-Precharge;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing once per clock
cycle; Address and control inputs changing once every two clock cycles;
OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); I
OUT
= 0mA; Address and control
inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
Power-down mode;
t
CK =
t
CK(MIN); CKE=LOW;
IDLE STANDBY CURRENNT: CS# = HIGH; All banks idle;
t
CK =
t
CK
(MIN); CKE = HIGH; Address and other control inputs changing once per
clock cycle. V
IN
= V
REF
for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
Power-down mode;
t
CK =
t
CK (MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank;
Active-Precharge;
t
RC =
t
RAS (MAX);
t
CK =
t
CK (MIN); DQ, DM, and
DQS inputs changing twice per clock cycle; Address and other control
inputs changing once per clock cycle.
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank
active; Address and control inputs changing once per clock cycle;
t
CK =
t
CK (MIN); I
OUT
= 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank
active; Address and control inputs changing once per clock cycle;
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
t
AUTO REFRESH CURRENT
RC = tRFC (MIN)
SELF REFRESH CURRENT (Part number ‘R’ only)
OPERATING CURRENT: Four bank interleaving READs (BL = 4) with
auto precharge,
t
RC =
t
RC (MIN);
t
CK =
t
RC (MIN); Address and control
inputs change only during Active, READ, or WRITE commands.
SYMBOL
I
DD
0
-75
105
-8
100
UNITS
mA
NOTES
22, 48
I
DD
1
120
115
mA
22, 48
I
DD
2
P
I
DD
2
N
10
50
10
45
mA
mA
23, 32,
50
51
I
DD
3
P
I
DD
3
N
18
50
18
45
mA
mA
23, 32,
50
22
I
DD
4
R
120
110
mA
22, 48
I
DD
4
W
120
110
mA
22
I
DD
5
I
DD
7
I
DD
8
250
2
330
225
2
285
mA
mA
mA
22, 50
11
22, 49
PDF: 09005aef80505d1b / Source: 09005aef80469e44
128Mb: x4, x8, x16 DDR SDRAM
Rev: 11/23/2004
5
www.spectek.com
SpecTek reserves the right to change products or specifications
without notice.
©
2001, 2002, 2004 SpecTek
