INTEGRATED CIRCUITS
DATA SHEET
SAA7182; SAA7183
Digital Video Encoder
(EURO-DENC)
Preliminary specification
Supersedes data of 1995 Sep 19
File under Integrated Circuits, IC22
1996 Jul 08
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
FEATURES
•
CMOS 5 V device
•
Digital PAL/NTSC/SECAM encoder
•
System pixel frequency 13.5 MHz
•
Accepts MPEG decoded data on 8-bit wide input port.
Input data format Cb, Y, Cr etc. or Y and Cb, Cr on
16 lines (“CCIR
656”)
•
Three DACs for CVBS, Y and C operating at 27 MHz
with 10-bit resolution
•
Three DACs for RGB operating at 27 MHz with 9-bit
resolution, RGB sync on CVBS and Y
•
CVBS, Y, C and RGB output simultaneously
•
Closed captioning and teletext encoding including
sequencer and filter
•
On-chip YUV to RGB matrix
•
Fast I
2
C-bus control port (400 kHz)
•
Encoder can be master or slave
•
Programmable horizontal and vertical input
synchronization phase
•
Programmable horizontal sync output phase
•
Internal Colour Bar Generator (CBG)
•
Overlay with Look-Up Tables (LUTs) 8
×
3 bytes
•
Macrovision Pay-per-View protection system as option,
also used for RGB output
This applies to SAA7183 only. The device is protected
by USA patent numbers 461603, 4577216 and 4819098
and other intellectual property rights.
QUICK REFERENCE DATA
SYMBOL
V
DDA
V
DDD
I
DDA
I
DDD
V
i
V
o(p-p)
R
L
ILE
DLE
T
amb
analog supply voltage
digital supply voltage
analog supply current
digital supply current
input signal voltage levels
analog output signal voltages Y, C, CVBS and RGB
without load (peak-to-peak value)
load resistance
LF integral linearity error
LF differential linearity error
operating ambient temperature
−
80
−
−
0
PARAMETER
SAA7182; SAA7183
Use of the Macrovision anti-copy process in the device
is licensed for non-commercial home use only. Reverse
engineering or disassembly is prohibited. Please
contact your nearest Philips Semiconductor sales office
for more information
•
Controlled rise/fall times of output syncs and blanking
•
Down-mode of DACs
•
PLCC84 package.
GENERAL DESCRIPTION
The SAA7182; SAA7183 encodes digital YUV video data
to an NTSC, PAL, SECAM CVBS or S-Video signal and
also RGB.
The circuit accepts CCIR compatible YUV data with
720 active pixels per line in 4 : 2 : 2 multiplexed formats,
for example MPEG decoded data. It includes a sync/clock
generator and on-chip Digital-to-Analog Converters
(DACs).
The circuit is compatible to the DIG-TV2 chip family.
MIN.
4.75
4.75
−
−
TYP.
5.0
5.0
90
220
2
−
−
−
−
MAX.
5.25
5.25
110
250
−
−
±2
±1
+70
V
V
UNIT
mA
mA
V
Ω
LSB
LSB
°C
TTL compatible
1996 Jul 08
2
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
SAA7182WP
SAA7183WP
BLOCK DIAGRAM
PLCC84
PLCC84
DESCRIPTION
plastic leaded chip carrier; 84 leads
plastic leaded chip carrier; 84 leads
SAA7182; SAA7183
VERSION
SOT189-2
SOT189-2
handbook, full pagewidth
RTCI
RESET SDA SCL SA
RCV1
TTXRQ XTALO
CREF
LLC
RCV2
CDIR
XTALI
Y/C/CVBS
VDDA4
to
VrefH2
VDDA7
75
68
64, 70,
72, 74
1
84
83
4
I
2
C-bus
control
8
37
50 35 36 20 47 45 44 48
I
2
C-BUS
INTERFACE
8
I
2
C-bus
control
SECAM
PROCESSOR
SYNC
CLOCK
I
2
C-bus
control
73
OUTPUT
INTERFACE
D
A
71
69
CHROMA
67
76
52
8
I
2
C-bus
control
61
Y
CbCr
RGB
PROCESSOR
D
A
58
55
CVBS
Y
DP0
to DP7
MP7
to MP0
OVL2
to OVL0
KEY
10 to 13
16 to 19
8
25 to 28
31 to 34
8
6 to 8
3
9
DbDr
Y
Y
ENCODER
CbCr
C
clock
and timing
8
DATA
MANAGER
8
I
2
C-bus
control
I
2
C-bus
control
internal
control bus
8
I
2
C-bus
control
VSSA
VrefL2
VrefL1
TTX
21
3
SAA7182
SAA7183
RED
GREEN
BLUE
3, 15, 24,
30, 39, 42,
51, 79, 81
VSSD1
to
VSSD9
5, 14, 22,
29, 38, 41,
49, 80, 82
VDDD1
to
VDDD9
2, 23, 40, 43,
46, 56, 59,
62, 65, 66
n.c.
78
SP
77
AP
53
VrefH1
63
54,
57, 60
VDDA1
to
VDDA3
MGB696
IRGB
Fig.1 Block diagram.
1996 Jul 08
3
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
PINNING
SYMBOL
RESET
n.c.
V
SSD1
SA
V
DDD1
OVL2
OVL1
OVL0
KEY
DP0
DP1
DP2
DP3
V
DDD2
V
SSD2
DP4
DP5
DP6
DP7
TTXRQ
TTX
V
DDD3
n.c.
V
SSD3
MP7
MP6
MP5
MP4
V
DDD4
V
SSD4
MP3
MP2
MP1
MP0
RCV1
RCV2
RTCI
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
digital supply voltage 4
digital ground 4
digital supply voltage 2
digital ground 2
Key input for OVL. When HIGH it selects OVL input.
DESCRIPTION
SAA7182; SAA7183
Reset input, active LOW. After reset is applied, all digital I/Os are in input mode.
The I
2
C-bus receiver waits for the START condition.
not connected
digital ground 1
The I
2
C-bus slave address select pin. LOW: slave address = 88H, HIGH = 8CH.
digital supply voltage 1
3-bit overlay data input. This is the index for the internal look-up table.
Lower 4 bits of the data port. Input for multiplexed Cb, Cr data if 16 line input mode is used.
Upper 4 bits of the data port. Input for multiplexed Cb, Cr data if 16 line input mode is used.
Teletext request output, indicating when the bitstream is valid.
Teletext bitstream input.
digital supply voltage 3
not connected
digital ground 3
Upper 4 bits of MPEG port. It is an input for
“CCIR 656”
style multiplexed Cb, Y, Cr data, or
input for Y data only, if 16 line input mode is used.
Lower 4 bits of MPEG port. It is an input for
“CCIR 656”
style multiplexed Cb, Y, Cr data, or
input for Y data only, if 16 line input mode is used.
Raster Control 1 for video port. This pin receives/provides a VS/FS/FSEQ signal.
Raster Control 2 for video port. This pin provides an HS pulse of programmable length or
receives an HS pulse.
Real Time Control Input. If the LLC clock is provided by an
SAA7111
or
SAA7151B,
RTCI
should be connected to the RTCO pin of the respective decoder to improve the signal quality.
1996 Jul 08
4
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
SAA7182; SAA7183
SYMBOL
V
DDD5
V
SSD5
n.c.
V
DDD6
V
SSD6
n.c.
XTALI
XTALO
n.c.
CREF
LLC
V
DDD7
CDIR
PIN
38
39
40
41
42
43
44
45
46
47
48
49
50
digital supply voltage 5
digital ground 5
not connected
digital supply voltage 6
digital ground 6
not connected
DESCRIPTION
Crystal oscillator input (from crystal). If the oscillator is not used, this pin should be connected
to ground.
Crystal oscillator output (to crystal).
not connected
Clock Reference signal. This is the clock qualifier for DIG-TV2 compatible signals.
Line-Locked Clock. This is the 27 MHz master clock for the encoder. The I/O direction is set
by the CDIR pin.
digital supply voltage 7
Clock direction. If the CDIR input is HIGH, the circuit receives a clock and optional CREF
signal, otherwise if CDIR is LOW CREF and LLC are generated by the internal crystal
oscillator.
digital ground 7
Lower reference voltage 1 input for the RGB DACs, connect to V
SSA
.
Upper reference voltage 1 input for the RGB DACs, connect via 100 nF capacitor to V
SSA.
Analog supply voltage 1 for the RGB DACs.
Analog output of the BLUE component.
not connected
Analog supply voltage 2 for the RGB DACs.
Analog output of the GREEN component.
not connected
Analog supply voltage 3 for the RGB DACs.
Analog output of the RED component.
not connected
Current input for RGB amplifiers, connected via 15 kΩ resistor to V
DDA
.
Analog supply voltage 4 for the Y/C/CVBS DACs.
not connected
not connected
Analog ground for the DACs.
Current input for the Y/C/CVBS amplifiers, connected via 15 kΩ resistor to V
DDA
.
Analog output of the chrominance signal.
Analog supply voltage 5 for the Y/C/CVBS DACs.
Analog output of the luminance signal.
Analog supply voltage 6 for the Y/C/CVBS DACs.
Analog output of the CVBS signal.
V
SSD7
V
refL1
V
refH1
V
DDA1
BLUE
n.c.
V
DDA2
GREEN
n.c.
V
DDA3
RED
n.c.
I
RGB
V
DDA4
n.c.
n.c.
V
SSA
I
Y/C/CVBS
CHROMA
V
DDA5
Y
V
DDA6
CVBS
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
1996 Jul 08
5
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