SC16C652B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte
FIFOs and infrared (IrDA) encoder/decoder
Rev. 04 — 1 September 2005
Product data sheet
1. General description
The SC16C652B is a 2 channel Universal Asynchronous Receiver and Transmitter
(UART) used for serial data communications. Its principal function is to convert parallel
data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s.
The SC16C652B is pin compatible with the SC16C2550. It will power-up to be functionally
equivalent to the 16C2450. The SC16C652B provides enhanced UART functions with
32-byte FIFOs, modem control interface, DMA mode data transfer, and IrDA
encoder/decoder. The DMA mode data transfer is controlled by the FIFO trigger levels
and the TXRDY and RXRDY signals. On-board status registers provide the user with error
indications and operational status. System interrupts and modem control features may be
tailored by software to meet specific user requirements. An internal loop-back capability
allows on-board diagnostics. Independent programmable baud rate generators are
provided to select transmit and receive baud rates.
The SC16C652B operates at 5 V, 3.3 V and 2.5 V and the industrial temperature range,
and is available in plastic LQFP48 and very small (Micro-UART) HVQFN32 packages.
2. Features
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
2 channel UART
5 V, 3.3 V and 2.5 V operation
5 V tolerant inputs
Industrial temperature range (−40
°C
to +85
°C)
Pin and functionally compatible to 16C2450 in LQFP48 package, and software
compatible with industry standard 16C450, 16C550, and SC16C650
Up to 5 Mbit/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V
32-byte transmit FIFO to reduce the bandwidth requirement of the external CPU
32-byte receive FIFO with error flags to reduce the bandwidth requirement of the
external CPU
Independent transmit and receive UART control
Four selectable Receive and Transmit FIFO interrupt trigger levels
Automatic software (Xon/Xoff) and hardware (RTS/CTS) flow control
Programmable Xon/Xoff characters
Software selectable baud rate generator
Standard modem interface or infrared IrDA encoder/decoder interface
Supports IrDA version 1.0 (up to 115.2 kbit/s)
Sleep mode
Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break)
Philips Semiconductors
SC16C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
s
Transmit, Receive, Line Status, and Data Set interrupts independently controlled
s
Fully programmable character formatting:
x
5-bit, 6-bit, 7-bit, or 8-bit characters
x
Even, odd, or no-parity formats
x
1, 1
1
⁄
2
, or 2-stop bit
x
Baud generation (DC to 5 Mbit/s)
s
False start-bit detection
s
Complete status reporting capabilities
s
3-state output TTL drive capabilities for bi-directional data bus and control bus
s
Line break generation and detection
s
Internal diagnostic capabilities:
x
Loop-back controls for communications link fault isolation
s
Prioritized interrupt system controls
s
Modem control functions (CTS, RTS, DSR, DTR, RI, CD)
3. Ordering information
Table 1:
Ordering information
Package
Name
SC16C652BIB48
SC16C652BIBS
LQFP48
HVQFN32
Description
plastic low profile quad flat package; 48 leads; body 7
×
7
×
1.4 mm
plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5
×
5
×
0.85 mm
Version
SOT313-2
SOT617-1
Type number
SC16C652B_4
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 1 September 2005
2 of 43
Philips Semiconductors
SC16C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
4. Block diagram
SC16C652B
TRANSMIT
FIFO
REGISTER
DATA BUS
AND
CONTROL
LOGIC
FLOW
CONTROL
LOGIC
IR
ENCODER
TRANSMIT
SHIFT
REGISTER
TXA, TXB
D0 to D7
IOR
IOW
RESET
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
RECEIVE
FIFO
REGISTER
RECEIVE
SHIFT
REGISTER
RXA, RXB
A0 to A2
CSA
CSB
REGISTER
SELECT
LOGIC
FLOW
CONTROL
LOGIC
IR
DECODER
DTRA, DTRB
RTSA, RTSB
OP2A, OP2B
MODEM
CONTROL
LOGIC
INTA, INTB
TXRDYA, TXRDYB
RXRDYA, RXRDYB
INTERRUPT
CONTROL
LOGIC
CLOCK AND
BAUD RATE
GENERATOR
CTSA, CTSB
RIA, RIB
CDA, CDB
DSRA, DSRB
002aaa592
XTAL1
XTAL2
Fig 1. Block diagram of SC16C652B
SC16C652B_4
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 1 September 2005
3 of 43
Philips Semiconductors
SC16C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
5. Pinning information
5.1 Pinning
43 TXRDYA
39 DSRA
38 CTSA
40 CDA
42 V
CC
41 RIA
D5
D6
D7
RXB
RXA
TXRDYB
TXA
TXB
OP2B
1
2
3
4
5
6
7
8
9
37 n.c.
36 RESET
35 DTRB
34 DTRA
33 RTSA
32 OP2A
31 RXRDYA
30 INTA
29 INTB
28 A0
27 A1
26 A2
25 n.c.
n.c. 24
002aaa593
002aaa865
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
46 D2
IOW 15
48 D4
47 D3
45 D1
CDB 16
SC16C652BIB48
CSA 10
CSB 11
n.c. 12
XTAL1 13
XTAL2 14
GND 17
RXRDYB 18
IOR 19
DSRB 20
RIB 21
RTSB 22
CTSB 23
Fig 2. Pin configuration for LQFP48
44 D0
32 D5
31 D4
30 D3
29 D2
28 D1
D6
D7
RXB
RXA
TXA
TXB
OP2B
CSA
1
2
3
4
5
6
7
8
XTAL1 10
XTAL2 11
IOW 12
GND 13
IOR 14
RTSB 15
CTSB 16
9
27 D0
terminal 1
index area
26 V
CC
25 CTSA
24 RESET
23 RTSA
22 OP2A
21 INTA
20 INTB
19 A0
18 A1
17 A2
SC16C652BIBS
CSB
SC16C652B_4
Transparent top view
Fig 3. Pin configuration for HVQFN32
Product data sheet
Rev. 04 — 1 September 2005
4 of 43
Philips Semiconductors
SC16C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
5.2 Pin description
Table 2:
Symbol
A0
A1
A2
CDA
CDB
CSA
CSB
28
27
26
40
16
10
11
Pin description
Pin
LQFP48 HVQFN32
19
18
17
-
-
8
9
I
I
I
I
I
Address 0 select bit.
Internal register address selection.
Address 1 select bit.
Internal register address selection.
Address 2 select bit.
Internal register address selection.
Carrier Detect (active LOW).
These inputs are associated with individual UART
channels A through B. A logic 0 on this pin indicates that a carrier has been
detected by the modem for that channel.
Chip Select A, B (active LOW).
This function is associated with individual
channels, A through B. These pins enable data transfers between the user CPU
and the SC16C652B for the channel(s) addressed. Individual UART sections (A, B)
are addressed by providing a logic 0 on the respective CSA, CSB pin.
Clear to Send (active LOW).
These inputs are associated with individual UART
channels, A through B. A logic 0 on the CTS pin indicates the modem or data set is
ready to accept transmit data from the SC16C652B. Status can be tested by
reading MSR[4]. This pin has no effect on the UART’s transmit or receive
operation.
Data Set Ready (active LOW).
These inputs are associated with individual UART
channels, A through B. A logic 0 on this pin indicates the modem or data set is
powered-on and is ready for data exchange with the UART. This pin has no effect
on the UART’s transmit or receive operation.
Data Terminal Ready (active LOW).
These outputs are associated with individual
UART channels, A through B. A logic 0 on this pin indicates that the SC16C652B is
powered-on and ready. This pin can be controlled via the modem control register.
Writing a logic 1 to MCR[0] will set the DTR output to logic 0, enabling the modem.
This pin will be a logic 1 after writing a logic 0 to MCR[0], or after a reset. This pin
has no effect on the UART’s transmit or receive operation.
Data bus (bi-directional).
These pins are the 8-bit, 3-state data bus for
transferring information to or from the controlling CPU. D0 is the least significant bit
and the first data bit in a transmit or receive serial data stream.
Type Description
CTSA
CTSB
38
23
25
16
I
DSRA
DSRB
39
20
-
-
I
DTRA
DTRB
34
35
-
-
O
D0
D1
D2
D3
D4
D5
D6
D7
GND
INTA
INTB
44
45
46
47
48
1
2
3
17
30
29
27
28
29
30
31
32
1
2
13
21
20
I/O
I
O
Signal and power ground.
Interrupt A, B (3-state).
This function is associated with individual channel
interrupts, INTA, INTB. INTA, INTB are enabled when MCR bit 3 is set to a logic 1,
interrupts are enabled in the Interrupt Enable Register (IER), and is active when an
interrupt condition exists. Interrupt conditions include: receiver errors, available
receiver buffer data, transmit buffer empty, or when a modem status flag is
detected.
Read strobe (active LOW strobe).
A logic 0 transition on this pin will load the
contents of an internal register defined by address bits A0 to A2 onto the
SC16C652B data bus (D0 to D7) for access by external CPU.
IOR
19
14
I
SC16C652B_4
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 1 September 2005
5 of 43
模拟电子
