SC16C750B
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
Rev. 03 — 13 December 2004
Product data
1. General description
The SC16C750B is a Universal Asynchronous Receiver and Transmitter (UART)
used for serial data communications. Its principal function is to convert parallel data
into serial data, and vice versa. The UART can handle serial data rates up to 3 Mbit/s.
The SC16C750B is pin compatible with the TL16C750 and it will power-up to be
functionally equivalent to the 16C450. Programming of control registers enables the
added features of the SC16C750B. Some of these added features are the 64-byte
receive and transmit FIFOs, automatic hardware flow control. The selectable
auto-flow control feature significantly reduces software overload and increases
system efficiency while in FIFO mode by automatically controlling serial data flow
using RTS output and CTS input signals. The SC16C750B also provides DMA mode
data transfers through FIFO trigger levels and the TXRDY and RXRDY signals.
On-board status registers provide the user with error indications, operational status,
and modem interface control. System interrupts may be tailored to meet user
requirements. An internal loop-back capability allows on-board diagnostics.
The SC16C750B operates at 5 V, 3.3 V and 2.5 V, the industrial temperature range
and is available in plastic PLCC44, LQFP64, and HVQFN32 packages.
2. Features
s
s
s
s
s
s
s
s
s
s
s
Single channel
5 V, 3.3 V and 2.5 V operation
5 V tolerant inputs
Industrial temperature range (−40
°C
to +85
°C)
After reset, all registers are identical to the typical 16C450 register set
Capable of running with all existing generic 16C450 software
Pin compatibility with the industry-standard ST16C450/550, TL16C450/550,
PC16C450/550. Software compatible with SC16C750 and TL16C750
Up to 3 Mbit/s transmit/receive operation at 5 V, 2 Mbit/s at 3.3 V, and 1 Mbit/s at
2.5 V
64 byte transmit FIFO
64 byte receive FIFO with error flags
Programmable auto-RTS and auto-CTS
x
In auto-CTS mode, CTS controls transmitter
x
In auto-RTS mode, RxFIFO contents and threshold control RTS
Automatic hardware flow control
Software selectable Baud Rate Generator
Four selectable Receive interrupt trigger levels
s
s
s
Philips Semiconductors
SC16C750B
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
s
Standard modem interface
s
Sleep mode
s
Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun
Break)
s
Independent receiver clock input
s
Transmit, Receive, Line Status, and Data Set interrupts independently controlled
s
Fully programmable character formatting:
x
5, 6, 7, or 8-bit characters
x
Even, Odd, or No-Parity formats
x
1, 1
1
⁄
2
, or 2-stop bit
x
Baud generation (DC to 3 Mbit/s)
s
False start-bit detection
s
Complete status reporting capabilities
s
3-State output TTL drive capabilities for bi-directional data bus and control bus
s
Line Break generation and detection
s
Internal diagnostic capabilities:
x
Loop-back controls for communications link fault isolation
s
Prioritized interrupt system controls
s
Modem control functions (CTS, RTS, DSR, DTR, RI, DCD).
3. Ordering information
Table 1:
Ordering information
Industrial: V
CC
= 2.5 V, 3.3 V or 5 V
±
10%; T
amb
=
−
40
°
C to +85
°
C.
Type number
SC16C750BIA44
SC16C750BIB64
SC16C750BIBS
Package
Name
PLCC44
LQFP64
HVQFN32
Description
plastic leaded chip carrier; 44 leads
plastic low profile quad flat package; 64 leads; 10
×
10
×
1.4 mm
plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5
×
5
×
0.85 mm
Version
SOT187-2
SOT314-2
SOT617-1
9397 750 14453
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 13 December 2004
2 of 44
Philips Semiconductors
SC16C750B
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
4. Block diagram
SC16C750B
TRANSMIT
FIFO
REGISTERS
D0–D7
IOR, IOR
IOW, IOW
RESET
DATA BUS
AND
CONTROL LOGIC
FLOW
CONTROL
LOGIC
TRANSMIT
SHIFT
REGISTER
TX
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
RECEIVE
FIFO
REGISTERS
RECEIVE
SHIFT
REGISTER
RX
A0–A2
CS0, CS1, CS2
AS
REGISTER
SELECT
LOGIC
FLOW
CONTROL
LOGIC
DDIS
DTR
RTS
OUT1, OUT2
MODEM
CONTROL
LOGIC
INTERRUPT
CONTROL
LOGIC
CLOCK AND
BAUD RATE
GENERATOR
INT
TXRDY
RXRDY
CTS
RI
DCD
DSR
002aaa588
XTAL1
RCLK
XTAL2
BAUDOUT
Fig 1. Block diagram.
9397 750 14453
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 13 December 2004
3 of 44
Philips Semiconductors
SC16C750B
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
5. Pinning information
5.1 Pinning
42 DCD
44 VCC
41 DSR
40 CTS
1 n.c.
6 D4
5 D3
4 D2
3 D1
2 D0
D5
D6
D7
7
8
9
43 RI
39 RESET
38 OUT1
37 DTR
36 RTS
35 OUT2
RCLK 10
RX 11
n.c. 12
TX 13
CS0 14
CS1 15
CS2 16
BAUDOUT 17
SC16C750BIA44
34 n.c.
33 INT
32 RXRDY
31 A0
30 A1
29 A2
XTAL1 18
XTAL2 19
IOW 20
IOW 21
GND 22
n.c. 23
IOR 24
IOR 25
DDIS 26
TXRDY 27
AS 28
002aaa589
Fig 2. PLCC44 pin configuration.
27 V
CC
26 DSR
32 D4
31 D3
30 D2
29 D1
D5
D6
D7
RCLK
RX
TX
CS
BAUDOUT
28 D0
terminal 1
index area
1
2
3
4
5
6
7
8
25 CTS
24 RESET
23 OUT
22 DTR
21 RTS
20 INT
19 RXRDY
18 A0
17 A1
A2 16
002aaa949
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
SC16C750BIBS
(top view)
XTAL2 10
IOW 11
n.c. 12
GND 13
IOR 14
Fig 3. HVQFN32 pin configuration (top view).
9397 750 14453
Product data
Rev. 03 — 13 December 2004
TXRDY 15
XTAL1
9
4 of 44
Philips Semiconductors
SC16C750B
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
64 BAUDOUT
54 RCLK
62 CS2
61 CS1
59 CS0
63 n.c.
60 n.c.
57 n.c.
56 n.c.
53 n.c.
XTAL1 1
XTAL2 2
n.c. 3
IOW 4
n.c. 5
IOW 6
n.c. 7
GND 8
49 n.c.
48 D4
47 n.c.
46 D3
45 D2
44 n.c.
43 D1
42 D0
41 n.c.
40 VCC
39 n.c.
38 RI
37 n.c.
36 DCD
35 DSR
34 n.c.
33 CTS
RESET 32
002aaa590
55 RX
58 TX
52 D7
51 D6
OUT1 30
SC16C750BIB64
IOR 9
IOR 10
n.c. 11
DDIS 12
TXRDY 13
n.c. 14
AS 15
n.c. 16
A2 17
A1 18
n.c. 19
A0 20
RXRDY 21
n.c. 22
INT 23
n.c. 24
OUT2 25
RTS 26
n.c. 27
DTR 28
n.c. 29
n.c. 31
Fig 4. LQFP64 pin configuration.
5.2 Pin description
Table 2:
Symbol
A2-A0
Pin description
Pin
PLCC44 LQFP64
29, 30,
31
28
17, 18, 20
HVQFN32
16, 17, 18 I
Register select.
A0-A2 are used during read and write operations
to select the UART register to read from or write to. Refer to
Table 3
for register addresses and refer to AS description.
Address strobe.
When AS is active (LOW), A0, A1, and A2 and
CS0, CS1, and CS2 drive the internal select logic directly; when AS
is HIGH, the register select and chip select signals are held at the
logic levels they were in when the LOW-to-HIGH transition of AS
occurred.
Baud out.
BAUDOUT is a 16× clock signal for the transmitter
section of the UART. The clock rate is established by the reference
oscillator frequency divided by a divisor specified in the baud
generator divisor latches. BAUDOUT may also be used for the
receiver section by tying this output to RCLK.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Type
Description
AS
15
-
I
BAUDOUT 17
64
8
O
9397 750 14453
Product data
Rev. 03 — 13 December 2004
50 D5
5 of 44
