Si5383/84 Rev D Data Sheet
Network Synchronizer Clocks Supporting 1 PPS to 750 MHz
Inputs
The Si5383/84 combines the industry’s smallest footprint and lowest power network syn-
chronizer clock with unmatched frequency synthesis flexibility and ultra-low jitter. The
Si5383/84 is ideally suited for wireless backhaul, IP radio, small and macro cell wireless
communications systems, and data center switches requiring both traditional and packet
based network synchronization.
The three independent DSPLLs are individually configurable as a SyncE PLL, IEEE 1588
DCO, or a general-purpose PLL for processor/FPGA clocking. The Si5383/84 can also
be used in legacy SETS systems needing Stratum 3/3E compliance. In addition, locking
to a 1 PPS input frequency is available on DSPLL D. The DCO mode provides precise
timing adjustment to 1 part per trillion (ppt). The unique design of the Si5383/84 allows
the device to accept a TCXO/OCXO reference with a wide frequency range, and the ref-
erence clock jitter does not degrade the output performance. The Si5383/84 is configura-
ble via a serial interface and programming the Si5383/84 is easy with ClockBuilder Pro
software. Factory pre-programmed devices are also available.
Applications
• Synchronous Ethernet (SyncE) ITU-T G.8262 EEC Options 1 and 2
• Telecom Grand Master Clock (T-GM) as defined by ITU-T G.8273.1
• Telecom Boundary Clock and Slave Clock (T-BC, T-TSC) as defined by ITU-T G.
8273.2
• IEEE 1588 (PTP) slave clock synchronization
• Stratum 3/3E, G.812, G.813, GR-1244, GR-253 network synchronization
• 1 Hz/1 PPS Clock Multiplier
XTAL
OCXO/
TCXO
XA REFb
OSC
REF
KEY FEATURES
• One or three independent DSPLLs in a
single monolithic IC supporting flexible
SyncE/IEEE 1588 and SETS architectures
• Input frequency range:
• External crystal: 25-54 MHz
• REF clock: 5-250 MHz
• Diff clock: 8 kHz - 750 MHz
• LVCMOS clock: 1 PPS, 8 kHz - 250
MHz
• Output frequency range:
• Differential: 1 PPS, 100 Hz - 718.5 MHz
• LVCMOS: 1 PPS, 100 Hz - 250 MHz
• Ultra-low jitter of less than 150 fs
XB
Si5383/84
IN4
IN3
DSPLL
D
Si5384
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
IN1
IN0
÷FRAC
÷FRAC
I
2
C
FLASH
Control/
Status
DSPLL A
DSPLL C
÷INT
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Si5383
IN2
÷FRAC
Rev. 1.1
Si5383/84 Rev D Data Sheet
Feature List
1. Feature List
The Si5383/84 highlighted features are listed below.
• One or three DSPLLs in a single monolithic IC supporting
flexible SyncE/IEEE 1588 and SETS architectures
• Meets the requirements of:
• ITU-T G.8273.1 T-GM
• ITU-T G.8273.2 T-BC, T-TSC
• Synchronous Ethernet (SyncE) ITU-T G.8262 EEC Op-
tions 1 and 2
• ITU-T G.812 Type III, IV
• ITU-T G.813 Option 1
• Telcordia GR-1244, GR-253 (Stratum-3/3E)
• Each DSPLL generates any output frequency from any input
frequency
• Input frequency range:
• External crystal: 25 - 54 MHz
• REF clock: 5 - 250 MHz
• Diff clock: 8 kHz - 750 MHz
• LVCMOS clock: 1 PPS, 8 kHz - 250 MHz
• Output frequency range:
• Differential: 1 PPS, 100 Hz - 718.5 MHz
• LVCMOS: 1 PPS, 100 Hz - 250 MHz
• Pin or software controllable DCO on each DSPLL with typical
resolution to 1 ppt/step
• TCXO/OCXO reference input determines DSPLL free-run/hold-
over accuracy and stability
• Excellent jitter performance
• Programmable loop bandwidth per DSPLL:
• 1 PPS inputs: 1 mHz and 10 mHz
• All other inputs: 1 mHz to 4 kHz
• Highly configurable output drivers: LVDS, LVPECL, LVCMOS,
HCSL, CML
• Core voltage:
• VDD: 1.8 V ±5%
• VDDA: 3.3 V ±5%
• Independent output supply pins: 3.3 V, 2.5 V, or 1.8 V
• Built-in power supply filtering
• Status monitoring:
• LOS, LOL: 1 PPS-750 MHz
• OOF: 8 kHz-750 MHz
• I
2
C Serial Interface
• ClockBuilder
TM
Pro software tool simplifies device configura-
tion
• 5 input, 7 output, 56-pin LGA
• Temperature range: –40 to +85 °C
• Pb-free, RoHS-6 compliant
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Rev. 1.1 | 2
Si5383/84 Rev D Data Sheet
Ordering Guide
2. Ordering Guide
Table 2.1. Ordering Guide
Ordering Part Number (OPN)
1,2
Si5383A-Dxxxxx-GM
Si5383B-Dxxxxx-GM
Si5384A-Dxxxxx-GM
Si5384B-Dxxxxx-GM
Si5383-D-EVB
3
SiOCXO1-EVB
—
—
1
# of DSPLLs
3
Maximum Out-
put Frequency
718.5 MHz
350 MHz
718.5 MHz
350 MHz
—
—
Evaluation Board
OCXO Evaluation
Board
—
—
—
—
Package
56-Lead 8×8 LGA
RoHS-6, Pb-
Free
Yes
Temperature Range
–40 to 85 °C
Notes:
1. Add an R at the end of the OPN to denote tape and reel ordering options.
2. Custom, factory preprogrammed devices are available as well as unconfigured base devices. See figures below for 5-digit numer-
ical sequence nomenclature.
3. The Si5383-D-EVB ships with an SiOCXO1-EVB board included. Additional SiOCXO1-EVB boards may be ordered separately if
needed.
2.1 Ordering Part Number Fields
Si538fg-R00xxx-GM
Timing product family
f = Network Sync
family
member (3, 4)
g = Device
grade
(A, B)
Product Die
Revision
(D)
Base device indicator*
Firmware revision indicator**
Package, ambient temperature range (LGA, -40°C to + 85°C)
* Firmware is preprogrammed into base devices, but no configuration settings are present in the device
** 3 digits corresponding to the firmware revision preprogrammed into base devices
Figure 2.1. Ordering Guide Part Number Fields for Base Devices
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Rev. 1.1 | 3
Si5383/84 Rev D Data Sheet
Ordering Guide
Si538fg-Rxxxxx-GM
Timing product family
f = Network Sync
family
member (3, 4)
g = Device
grade
(A, B)
Product Die
Revision
(D)
Custom ordering part number (OPN) sequence ID**
Package, ambient temperature range (LGA, -40°C to +85°C)
** 5 digits; assigned by ClockBuilder Pro for custom, factory-preprogrammed OPN devices.
The firmware revision for custom OPN devices is determined by ClockBuilder Pro when a custom part number is created.
Figure 2.2. Ordering Guide Part Number Fields for Custom OPN Devices
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Rev. 1.1 | 4
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Ordering Guide
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
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. 3
2.1 Ordering Part Number Fields .
3. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Standards Compliance .
3.2 Frequency Configuration
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. 7
. 7
. 7
. 7
. 7
. 7
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8
8
8
9
9
9
3.3 DSPLL Loop Bandwidth in Standard Input Mode
3.3.1 Fastlock Feature . . . . . . . . . .
3.4 DSPLL Loop Bandwidth in 1 PPS Mode
3.4.1 Smartlock Feature . . . . . .
3.5 Modes of Operation . .
3.5.1 Initialization and Reset
3.5.2 Free-run Mode . .
3.5.3 Lock Acquisition Mode
3.5.4 Locked Mode . . .
3.5.5 Holdover Mode . .
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3.6 Digitally-Controlled Oscillator (DCO) Mode . . . . . . . . . .
3.6.1 Frequency Increment/Decrement Using Pin Controls (FINC, FDEC)
3.6.2 Frequency Increment/Decrement Using the Serial Interface . . .
3.7 External Reference (XA/XB, REF/REFb) .
3.7.1 External Crystal (XA/XB) . . . . .
3.7.2 External Reference (REF/REFb) . .
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.10
.10
.11
.11
.12
.13
.14
.14
.14
.14
.15
.15
.16
.16
.16
.17
.17
.17
.18
.18
.18
.19
.21
.21
.22
.23
3.8 Inputs (IN0, IN1, IN2, IN3, IN4) . . . . . . . . . . . .
3.8.1 Input Selection . . . . . . . . . . . . . . . .
3.8.2 Manual Input Selection . . . . . . . . . . . . . .
3.8.3 Automatic Input Selection in Standard Input Mode . . . .
3.8.4 Input Configuration and Terminations . . . . . . . . .
3.8.5 Hitless Input Switching in Standard Input Mode . . . . .
3.8.6 Ramped Input Switching in Standard Input Mode . . . . .
3.8.7 Glitchless Input Switching . . . . . . . . . . . . .
3.8.8 Synchronizing to Gapped Input Clocks in Standard Input Mode
3.9 Fault Monitoring . . . .
3.9.1 Input LOS Detection. .
3.9.2 XA/XB LOS Detection .
3.9.3 OOF Detection . . .
3.9.4 Precision OOF Monitor .
3.9.5 Fast OOF Monitor . .
3.9.6 LOL Detection . . . .
3.9.7 Interrupt Pin (INTRb) .
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3.10 Outputs . . . . . . . .
3.10.1 Output Crosspoint . . .
3.10.2 Support For 1 Hz Output .
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单片机
