Si8430/31/35
U
L T R A
L
O W
P
O W E R
T
R I P L E
-C
H A N N E L
D
I G I TA L
I
S O L A T O R
Features
High-speed operation:
DC – 150 Mbps
Low propagation delay:
<10 ns typical
Wide Operating Supply Voltage:
2.75-5.5V
Ultra low power
5 V Operation:
I< 1.25 mA per channel at 1 Mbps
I< 2 mA per channel at 10 Mbps
I< 6 mA per channel at 100 Mbps
2.75 V Operation:
I< 1.25 mA per channel at 1 Mbps
I< 2 mA per channel at 10 Mbps
I< 4 mA per channel at 100 Mbps
Pin Assignments
Precise timing:
2 ns pulse width distortion
1 ns channel-channel matching
2 ns pulse width skew
Up to 2500 V
RMS
isolation
Transient Immunity: 25 kV/µs
Tri-state outputs with ENABLE
control
DC correct
No start-up initialization required
<30 µs startup time
High temperature operation:
125 °C at 150 Mbps
Wide body and narrow body SOIC-
16 packages
V
DD1
GND1
A1
A2
A3
NC
EN1/NC
GND1
Wide Body SOIC
16
1
2
15
3
14
4
13
5
12
11
6
7
10
8
9
Top View
V
DD2
GND2
B1
B2
B3
NC
EN2/NC
GND2
Applications
Isolated switch mode supplies
Isolated ADC, DAC
Motor control
Power factor correction systems
Safety Regulatory Approvals*
UL recognition: 2500 V
RMS
for 1
VDE certification conformity
IEC 60747-5-2
Minute per UL1577
(VDE0884 Part 2)
CSA component acceptance notice
Narrow Body SOIC
V
DD1
1
16
V
DD2
GND1
2
15
GND2
A1
3
14
B1
A2
4
13
B2
A3
5
12
B3
NC
6
11
NC
EN1/NC
7
10
EN2/NC
GND1
8
9
GND2
Top View
Description
Silicon Lab's family of ultra low power digital isolators are CMOS devices
that employ an RF coupler to transmit digital information across an isolation
barrier. Very high speed operation at low power levels is achieved. These
parts are available in 16-pin wide body and narrow body SOIC packages.
Two speed grade options (1 and 150 Mbps) are available and achieve typical
propagation delay of less than 10 ns.
Block Diagram
Si8430/35
Si8431
A1
A2
A3
NC
B1
B2
B3
EN2/NC
A1
A2
A3
EN1
B1
B2
B3
EN2
*Note:
Pending.
Rev. 0.34 1/09
Copyright © 2009 by Silicon Laboratories
Si8430/31/35
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si8430/31/35
2
Rev. 0.34
Si8430/31/35
T
ABLE O F
C
ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Performance Characteristics* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3. Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1. Supply Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2. Input and Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3. Enable (EN1, EN2) Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.4. RF Radiated Emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.5. RF Immunity and Common Mode Transient Immunity . . . . . . . . . . . . . . . . . . . . . . . 23
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Rev. 0.34
3
Si8430/31/35
1. Electrical Specifications
Table 1. Electrical Characteristics
1
(V
DD1
= 5 V, V
DD2
= 5 V, T
A
= –40 to 125 ºC; applies to narrow and wide-body SOIC packages)
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Enable Input High Current
Enable Input Low Current
Si8430Ax, Bx and Si8435Bx
V
DD1
V
DD2
V
DD1
V
DD2
Si8431Ax, Bx
V
DD1
V
DD2
V
DD1
V
DD2
Si8430Ax, Bx
V
DD1
V
DD2
Si8431Ax, Bx
V
DD1
V
DD2
Si8430Bx, Si8435Bx
V
DD1
V
DD2
Si8431Bx
V
DD1
V
DD2
Symbol
V
IH
V
IL
V
OH
V
OL
I
L
I
ENH
I
ENL
Test Condition
Min
2.0
—
Typ
—
—
4.8
0.2
—
2
2
Max
—
0.8
—
0.4
±10
—
—
Unit
V
V
V
V
µA
µA
µA
loh = –4 mA
lol = 4 mA
V
ENx
= V
IH
V
ENx
= V
IL
V
DD1
,V
DD2
– 0.4
—
—
—
—
DC Supply Current
(All inputs 0 V or at Supply)
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
—
—
—
—
1
2
4
2
2
2
4
3
2
4
8
4
4
4
8
6
mA
mA
1 Mbps Supply Current
(All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
—
—
—
—
3
3
3
3
5
5
6
6
mA
mA
100 Mbps Supply Current
(All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
—
—
—
—
4
15
8
12
8
23
12
18
mA
mA
4
Rev. 0.34
Si8430/31/35
Table 1. Electrical Characteristics
1
(Continued)
(V
DD1
= 5 V, V
DD2
= 5 V, T
A
= –40 to 125 ºC; applies to narrow and wide-body SOIC packages)
Parameter
Si843xA
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
|t
PLH
- t
PHL
|
Symbol
Test Condition
Timing Characteristics
Min
Typ
Max
Unit
0
—
t
PHL
, t
PLH
PWD
t
PSK(P-P)
t
PSK
See Figure 2
See Figure 2
—
—
—
—
0
—
t
PHL
, t
PLH
PWD
t
PSK(P-P)
t
PSK
t
r
t
f
CMTI
t
en1
t
en2
t
SU
C
L
= 15 pF
See Figure 2
C
L
= 15 pF
See Figure 2
V
I
= V
DD
or 0 V
See Figure 1
See Figure 1
See Figure 2
See Figure 2
5
—
—
—
—
—
20
—
—
—
—
—
—
—
—
—
—
—
8
—
—
—
2
2
25
9
9
30
1
250
35
25
40
35
150
6
15
3
10
3
—
—
—
—
—
—
Mbps
ns
ns
ns
ns
ns
Mbps
ns
ns
ns
ns
ns
ns
ns
kV/µs
ns
ns
µs
Propagation Delay Skew
2
Channel-Channel Skew
Si843xB
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
Pulse Width Distortion
|t
PLH
- t
PHL
|
Propagation Delay Skew
2
Channel-Channel Skew
For All Models
Output Rise Time
Output Fall Time
Common Mode Transient
Immunity
Enable to Data Valid
Enable to Data Tri-State
Start-up Time
3
Notes:
1.
Electrical specification values are preliminary. Various specifications will be adjusted to reflect actual performance as
final product characterization data becomes available.
2.
t
PSK(P-P)
is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
3.
Start-up time is the time period from the application of power to valid data at the output.
Rev. 0.34
5
