SL74HC393
Dual 4-Stage Binary Ripple Counter
High-Performance Silicon-Gate CMOS
The SL74HC393 is identical in pinout to the LS/ALS393. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device consists of two independent 4-bit binary ripple
counters with parallel outputs from each counter stage. A÷256 counter
can be obtained by cascading the two binary counters.
Internal flip-flops are triggered by high-to-low transitions of the
clock input. Reset for the counters is asynchronous and active-high.
State changes of the Q outputs do not occur simultaneously becaue of
internal ripple delays. Therefore, decoded output signals are subject to
decoding spikes and should not be used as clocks or as strobes except
when gated with the Clock of the SL74HC393.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0
µA
•
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC393N Plastic
SL74HC393D SOIC
T
A
= -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Clock
X
PIN 14 =V
CC
PIN 7 = GND
H
L
Reset
H
L
L
L
L
X = don’t care
L
No Change
No Change
No Change
Advance to Next
State
Outputs
SLS
System Logic
Semiconductor
SL74HC393
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-1.5 to V
CC
+1.5
-0.5 to V
CC
+0.5
±20
±25
±50
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
V
CC
=2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
Min
2.0
0
-55
0
0
0
Max
6.0
V
CC
+125
1000
500
400
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND≤(V
IN
or V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ).
CC
Unused outputs must be left open.
SLS
System Logic
Semiconductor
SL74HC393
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
Parameter
Test Conditions
V
Guaranteed Limit
25
°C
to
-55°C
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
8.0
≤85
°C
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1.0
80
≤125
°C
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1.0
160
µA
µA
V
Unit
V
IH
Minimum High-Level
Input Voltage
Maximum Low -Level
Input Voltage
Minimum High-Level
Output Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
≤
20
µA
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
≤
20
µA
V
IN
=V
IH
or V
IL
I
OUT
≤
20
µA
V
IN
=V
IH
or V
IL
I
OUT
≤
4.0 mA
I
OUT
≤
5.2 mA
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
V
V
IL
V
V
OH
V
V
OL
Maximum Low-Level
Output Voltage
V
IN
=V
IH
or V
IL
I
OUT
≤
20
µA
V
IN
=V
IH
or V
IL
I
OUT
≤
4.0 mA
I
OUT
≤
5.2 mA
I
IN
I
CC
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
(per Package)
V
IN
=V
CC
or GND
V
IN
=V
CC
or GND
I
OUT
=0µA
SLS
System Logic
Semiconductor
SL74HC393
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
f
max
Parameter
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 3)
Maximum Propagation Delay, Clock to Q1
(Figures 1 and 3)
Maximum Propagation Delay, Clock to Q2
(Figures 1 and 3)
Maximum Propagation Delay, Clock to Q3
(Figures 1 and 3)
Maximum Propagation Delay, Clock to Q4
(Figures 1 and 3)
Maximum Propagation Delay, Reset to any Q
(Figures 2 and 3)
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
Maximum Input Capacitance
Power Dissipation Capacitance (Per Counter)
C
PD
Used to determine the no-load dynamic power
consumption: P
D
=C
PD
V
CC2
f+I
CC
V
CC
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
-
Guaranteed Limit
25
°C
to
-55°C
5.4
27
32
120
24
20
190
38
32
240
48
41
290
58
49
165
33
28
75
15
13
10
≤85°C
4.4
22
26
150
30
26
240
48
41
300
60
51
365
73
62
205
41
35
95
19
16
10
≤125°C
3.6
18
21
180
36
31
285
57
48
360
72
61
435
87
74
250
50
43
110
22
19
10
Unit
MHz
t
PLH
, t
PHL
ns
t
PLH
, t
PHL
ns
t
PLH
, t
PHL
ns
t
PLH
, t
PHL
ns
t
PHL
ns
t
TLH
, t
THL
ns
C
IN
pF
Typical @25°C,V
CC
=5.0 V
40
pF
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
t
rec
Parameter
Minimum Recovery Time, Reset
Inactive to Clock (Figure 2)
Minimum Pulse Width, Clock (Figure
1)
Minimum Pulse Width, Set
(Figure 2)
Maximum Input Rise and Fall Times
(Figure 1)
System Logic
Semiconductor
Guaranteed Limit
25
°C
to-55°C
50
10
9
80
16
14
125
25
21
1000
500
400
≤85°C
65
13
11
100
20
17
155
31
26
1000
500
400
≤125°C
75
15
13
120
24
20
190
38
32
1000
500
400
Unit
ns
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
t
w
ns
t
w
ns
t
r
, t
f
ns
SLS
SL74HC393
6.0
400
400
400
SLS
System Logic
Semiconductor
