SL74HC4046
Phase-Locked Loop
High-Performance Silicon-Gate CMOS
The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LS/ALSTTL outputs.
The SL74HC4046 phase-locked loop contains three phase
comparators, a voltage-controlled oscillator (VCO) and unity gain op-
amp DEM
OUT
. The comparators have two common signal inputs,
COMP
IN
, and SIG
IN
. Input SIG
IN
and COMP
IN
can be used directly
coupled to large voltage signals, or indirectly coupled (with a series
capacitor to small voltage signals). The self-bias circuit adjusts small
voltage signals in the linear region of the amplifier. Phase comparator 1
(an exclusive OR gate) provides a digital error signal PC1
OUT
and
maintains 90 degrees phase shift at the center frequency between SIG
IN
and COMP
IN
signals (both at 50% duty cycle). Phase comparator 2
ORDERING INFORMATION
(with leading-edge sensing logic) provides digital error signals PC2
OUT
SL74HC4046N Plastic
and PCP
OUT
and maintains a 0 degree phase shift between SIG
IN
and
SL74HC4046D SOIC
COMP
IN
signals (duty cycle is immaterial). The linear VCO produces an
T
A
= -55° to 125° C for all packages
output signal VCO
OUT
whose frequency is determined by the voltage of
input VCO
IN
signal and the capacitor and resistors connected to pins
C1A, C1B, R1 and R2. The unity gain op-amp output DEM
OUT
with an external resistor is used where the VCO
IN
signal is needed but no loading can be tolerated. The inhibit input, when high, disables the VCO and all on-amps
to minimize standby power consumption.
Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication,
frequency discrimination, tone decoding, data synchronization and conditioning, voltage-to-frequency
conversion and motor speed control.
•
Low Power Consumption Characteristic of CMOS Device
PIN ASSIGNMENT
•
Operating Speeds Similary to LS/ALSTTL
•
Wide Operating Voltage Range: 3.0 to 6.0 V
•
Low Input Current: 1.0
µA
Maximum (except SIG
IN
and
COMP
IN
)
•
Low Quiescent Current: 80
µA
Maximum (VCO disabled)
•
High Noise Immunity Characteristic of CMOS Devices
•
Diode Protection on all Inputs
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
PCP
OUT
PC1
OUT
COMP
IN
VCO
OUT
INH
C1A
C1B
GND
VCO
IN
DEM
OUT
R1
R2
PC2
OUT
SIG
IN
PC3
OUT
V
CC
Name and Function
Phase Comparator Pulse Output
Phase Comparator 1 Output
Comparator Input
VCO Output
Inhibit Input
Capacitor C1 Connection A
Capacitor C1 Connection B
Ground (0 V) V
SS
VCO Input
Demodulator Output
Resistor R1 Connection
Resistor R2 Connection
Phase Comparator 2 Output
Signal Input
Phase Comparator 3 Output
Positive Supply Voltage
System Logic
Semiconductor
SLS
SL74HC4046
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-1.5 to V
CC
+1.5
-0.5 to V
CC
+0.5
±20
±25
±50
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND) VCO only
DC Supply Voltage (Referenced to GND) NON-VCO
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
V
CC
=2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
Min
3.0
2.0
0
-55
0
0
0
Max
6.0
6.0
V
CC
+125
1000
500
400
Unit
V
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND≤(V
IN
or V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ).
CC
Unused outputs must be left open.
SLS
System Logic
Semiconductor
SL74HC4046
[Phase Comparator Section]
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
Parameter
Test Conditions
V
Guaranteed Limit
25
°C
to
-55°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±3.0
±7.0
±18.0
±30.0
±0.5
≤85
°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±4.0
±9.0
±23.0
±38.0
±5.0
≤125
°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±5.0
±11.0
±27.0
±45.0
±10
µA
V
Unit
V
IH
Minimum High-Level
Input Voltage DC
Coupled
SIG
IN
, COMP
IN
Maximum Low -Level
Input Voltage DC
Coupled
SIG
IN
, COMP
IN
Minimum High-Level
Output Voltage
PCP
OUT
, PCn
OUT
V
OUT
= 0.1 V or V
CC
-0.1 V
I
OUT
≤
20
µA
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
3.0
4.5
6.0
6.0
V
V
IL
V
OUT
=0.1 V or V
CC
-0.1 V
I
OUT
≤
20
µA
V
V
OH
V
IN
=V
IH
or V
IL
I
OUT
≤
20
µA
V
IN
= V
IH
or V
IL
I
OUT
≤
4.0 mA
I
OUT
≤
5.2 mA
V
V
OL
Maximum Low-Level
Output Voltage Q
a
-Q
h
PCP
OUT
, PCn
OUT
V
IN
=V
IH
or V
IL
I
OUT
≤
20
µA
V
IN
= V
IH
or V
IL
I
OUT
≤
4.0 mA
I
OUT
≤
5.2 mA
I
IN
Maximum Input
Leakage Current
SIG
IN
, COMP
IN
Maximum Three-State
Leakage Current
PC2
OUT
Maximum Quiescent
Supply Current
(per Package)
(VCO disabled)
Pins 3,5 and 14 at V
CC
Pin 9 at GND; Input
Leacage at
Pin 3 and 14 to be
excluded
V
IN
=V
CC
or GND
I
OZ
Output in High-Impedance
State
V
IN
= V
IL
or V
IH
V
OUT
=V
CC
or GND
V
IN
=V
CC
or GND
I
OUT
=0µA
µA
I
CC
6.0
4.0
40
160
µA
SLS
System Logic
Semiconductor
SL74HC4046
[Phase Comparator Section]
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
t
PLH
, t
PHL
Parameter
Maximum Propagation Delay, SIG
IN
/COMP
IN
to
PC1
OUT
(Figure 1)
Maximum Propagation Delay, SIG
IN
/COMP
IN
to
PCP
OUT
(Figure 1)
Maximum Propagation Delay , SIG
IN
/COMP
IN
to
PC3
OUT
(Figure 1)
Maximum Propagation Delay , SIG
IN
/COMP
IN
Output Disable Time to PC2
OUT
(Figures 2 and 3)
Maximum Propagation Delay , SIG
IN
/COMP
IN
Output Enable Time to PC2
OUT
(Figures 2 and 3)
Maximum Output Transition Time (Figure 1)
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Guaranteed Limit
25
°C
to
-55°C
175
35
30
340
68
58
270
54
46
200
40
34
230
46
39
75
15
13
≤85°C
220
44
37
425
85
72
340
68
58
250
50
43
290
58
49
95
19
16
≤125°C
265
53
45
510
102
87
405
81
69
300
60
51
345
69
59
110
22
19
Unit
ns
t
PLH
, t
PHL
ns
t
PLH
, t
PHL
ns
t
PLZ
, t
PHZ
ns
t
PZL
, t
PZH
ns
t
TLH
, t
THL
ns
[VCO Section]
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
V
IH
Parameter
Minimum High-Level
Input Voltage INH
Maximum Low -Level
Input Voltage INH
Minimum High-Level
Output Voltage
VCO
OUT
Test Conditions
V
OUT
= 0.1 V or
V
CC
-0.1 V
I
OUT
≤
20
µA
V
OUT
=0.1 V or V
CC
-
0.1 V
I
OUT
≤
20
µA
V
IN
=V
IH
or V
IL
I
OUT
≤
20
µA
V
IN
= V
IH
or V
IL
I
OUT
≤
4.0 mA
I
OUT
≤
5.2 mA
V
OL
Maximum Low-Level
Output Voltage
VCO
OUT
V
IN
=V
IH
or V
IL
I
OUT
≤
20
µA
V
IN
= V
IH
or V
IL
I
OUT
≤
4.0 mA
I
OUT
≤
5.2 mA
System Logic
Semiconductor
Guaranteed Limit
25
°C
to-55°C
2.1
3.15
4.2
0.90
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
≤85°C
2.1
3.15
4.2
0.90
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
≤125°C
2.1
3.15
4.2
0.90
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
V
Unit
V
V
3.0
4.5
6.0
3.0
4.5
6.0
3.0
4.5
6.0
4.5
6.0
3.0
4.5
6.0
4.5
6.0
V
IL
V
V
OH
V
SLS
SL74HC4046
(continued)
SLS
System Logic
Semiconductor
