SL74LV138
3-TO-8 DECODER/DEMULTIPLEXER
By pinning SL74LV138 are compatible with SL74HC138 and
SL74HCT138 series. Input voltage levels are compatible with
standard CMOS ones.
•
Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL IC
S
•
Supply voltage range is from 1.2 to 5.5 V
•
Low input current: 1.0
µÀ;
0.1
µÀ
at Ò = 25
°Ñ
•
Output current 6 mÀ
•
Latch current is not less than 150 mÀ at Ò = 125
°Ñ
•
ESD acceptable values: than 2000 V as per HBM, and not less
than 200 V as per MM
BLOCK DIAGRAM
Y0
ORDERING INFORMATION
SL74LV138N Plastic DIP
SL74LV138D SOIC
T
A
= -40° to 125° C
for all packages
Y1
PIN ASSIGNMENT
A0
A1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Y2
Y3
A0
A2
CS2
A1
Y4
Cs3
CS1
Y7
GND
Y5
A2
Y6
CS3
Y7
CS2
CS1
FUNCTION TABLE
CS1
X
X
L
H
H
H
H
H
H
H
H
System Logic
Semiconductor
INPUTS
CS2 CS3 A2
X
H
X
H
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
A1
X
X
X
L
L
H
H
L
L
H
H
A0
X
X
X
L
H
L
H
L
H
L
H
Q0
H
H
H
L
H
H
H
H
H
H
H
Q1
H
H
H
H
L
H
H
H
H
H
H
Q2
H
H
H
H
H
L
H
H
H
H
H
OUTPUTS
Q3 Q4
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
Q5
H
H
H
H
H
H
H
H
L
H
H
Q6
H
H
H
H
H
H
H
H
H
L
H
Q7
H
H
H
H
H
H
H
H
H
H
L
SLS
SL74LV138
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
Iik
Iok
Io
Icc
I
GND
Tstg
P
D
Parameter
Supply voltage
Input diode current
Output diode current
Output current standard output
DC Vcc, standard output
GND current
Starage temperature range
Power dissipation per package:
DIP
SO
Rating
-0.5 to +7.0
±20
±50
±25
±50
±50
-65 to +150
750
500
Unit
V
mA
mA
mÀ
mÀ
mÀ
î
Conditions
V
I
<-0.5 V orV
I
>Vcc>+0.5 V
V
0
<-0.5 V or V
I
>Vcc>+0.5 V
-0.5 V<Vo<Vcc+0.5 V
Ñ
mW
Notes:
Power dissipation value decreases for:
DIP - 12 mW°C in the range from 70 to 125°Ñ
SO - 8 mW°C in the range from 70 to 125°Ñ
RECOMMENDED OPERATING CONDITIONS
Symbol
Vcc
V
I
Vî
T
t
r
,t
f
Parameter
Supply voltage
Input voltage
Output voltage
Ambient temperature range
Input rise and fall times
Min
1.2
0
0
-40
Max
5.5
Vcc
Vcc
+125
500
200
100
50
Unit
V
V
V
o
Conditions
C
Vcc= 1.0
Vcc= 2.0
Vcc= 2.7
Vcc= 3.6
÷
2.0 V
÷
2.7 V
÷
3.6 V
÷
5.5 V
ns/V
SLS
System Logic
Semiconductor
SL74LV138
DC CHARACTERISTICS
Sym
bol
Parameter
Vcñ
(V)
V
IH
HIGH level
input voltage
1.2
2.0
2.7 to 3.6
4.5 to 5.5
1.2
2.0
2.7 to 3.6
4.5 to 5.5
1.2
2.0
2.7
3.6
5.5
3.0
4.5
V
IH
I
O
=-100
µÀ
or
V
IL
Conditions
V
I
-40 to +25°C
Min
0.9
1.4
2.0
0.7 Vcc
-
-
-
-
1.05
1.85
2.55
3.45
5.35
2.48
3.70
Max
-
-
-
-
0.3
0.6
0.8
0.3 Vcc
-
-
-
-
-
-
-
Limits
+85
î
Ñ
Min
0.9
1.4
2.0
0.7 Vcc
-
-
-
-
1.0
1.8
2.5
3.4
5.3
2.40
3.60
Max
-
-
-
-
0.3
0.6
0.8
0.3 Vcc
-
-
-
-
-
-
-
+125
î
Ñ
Min
0.9
1.4
2.0
0.7 Vcc
-
-
-
-
1.0
1.8
2.5
3.4
5.3
2.20
3.50
Max
-
-
-
--
0.3
0.6
0.8
0.3 Vcc
-
-
-
-
-
-
-
V
Unit
V
IL
LOW level
output
voltage
V
V
OH
HIGH level
output
voltage
V
V
OH
HIGH level
output
voltage;
standard
outputs
V
OL
LOW level
output
voltage
V
IH
I
O
=-6 mA
or I
O
=-12 mA
V
IL
V
1.2
2.0
2.7
3.6
5.5
3.0
4.5
V
IH
I
O
=100µÀ
or
V
IL
-
-
-
-
-
-
-
0.15
0.15
0.15
0.15
0.15
0.33
0.40
-
-
-
-
-
-
-
0.2
0.2
0.2
0.2
0.2
0.40
0.55
-
-
-
-
-
-
-
0.2
0.2
0.2
0.2
0.2
0.50
0.65
V
V
OL
LOW level
output
voltage;
standard
outputs
I
I
Input leakage
current
Supply
current
Additional
supply
current per
input
V
IH
I
O
=6 mA
or I
O
=12 mA
V
IL
V
5.5
Vññ
or
GD
N
Vññ Io = 0
or
GD
N
-
±1.0
±1.0
-
±1.0
µÀ
Icc
5.5
8.0
80
160
µÀ
Icc
2.7 äî 3.6 V
I
= Vcc-0.6V
-
0.2
0.5
-
0.85
mA
SLS
System Logic
Semiconductor
SL74LV138
AC CHARACTERISICS
(C
L
=50 pF, R
L
=1 KΩ, t
LH
= t
HL
= 2.5 ns
Sym
bol
Parameter
Conditions
Vcc
-40 to +25°C
Min
t
PHL
, t
PLH
Propagation
from An to delay
Yn
1.2
2.0
2.7
3.0
4.5
1.2
2.0
2.7
3.0
4.5
5.0
V
I
= Vcc or
GND
-
-
-
-
-
-
-
-
-
-
Max
150
33
23
19
14
170
35
26
21
17
7.0
134
Limits
+85°C
Min
-
-
-
-
-
-
-
-
-
-
Max
150
36
26
21
16
170
39
29
23
19
+125°C
Min
-
-
-
-
-
-
-
-
-
-
Max
150
44
33
26
20
170
49
36
29
24
-
-
ns
Unit
t
PHL
, t
PLH
Propagation
from CS to delay
Yn
V
I
= Vcc or
GND
ns
C
I
C
PD
Input
capacitance
Power
dissipation
capacitance
per package
Ò=+25
î
Ñ
Ò=+25
î
Ñ
V
I
= Vcc or
GND
ns
ns
SLS
System Logic
Semiconductor
SL74LV138
Drawing of the chip
1.4 mm
15
14
13
12
11
10
On-chip marking
1.33 m m
16
1
74LV138
9
8
7
2
3
4
5
6
Pads allocation Table
Pad
number
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
coordinates (counted from lower left corner), mm
X
Y
0.1415
0.6270
0.1415
0.3880
1.1375
0.1515
0.4535
0.1190
0.6245
0.1190
0.7800
0.1190
0.9520
0.1180
1.2685
0.1185
1.2480
0.2960
1.2650
0.5160
1.2650
0.8430
1.2425
1.0820
1.2465
1.3165
0.9520
1.3120
0.7800
1.3110
0.6245
1.3110
Pad size, mm
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
SLS
System Logic
Semiconductor
