®
SP3508
Evaluation Board Manual
FEATURES
■
Easy Evaluation of SP3508 Multi-Protocol
Transceiver
■
Eight (8) Drivers and Eight (8) Receivers
■
Current Mode V.35 Drivers
■
Internal Line or Digital Loopback
■
Internal Transceiver Termination Resistors for
V.11 and V.35
■
Termination Network Disable Option
■
Fast 20Mbps Differential Transmission Rates
■
Adheres to CTR1/CTR2 Compliancy Requirements
■
Interface modes:
RS-232(V.28)
X.21(V.11)
RS-449/V.36(V.10&V.11)
EIA-530(V.10&V.11)
EIA-530A(V.10&V.11)
V.35(V.35&V.28)
DESCRIPTION
The SP3508 Evaluation Board is designed to analyze the SP3508 multi-protocol transceivers.
The evaluation board provides access points to all of the driver and receiver I/O pins so that
the user can measure electrical characteristics and waveforms of each signal. The SP3508
Evaluation Board also includes a DB-25 serial port connector which is configured to a EIA-530
pinout. This allows easy connections to other DTE or DCE systems as well as network
analyzers. The evaluation board also has a set of jumpers to allow the user to select the mode
of operation and test the data latch feature. Furthermore, the SP3508 Evaluation Board
provides the means to test both local and remote driver/receiver Loopback as well as evaluate
the SP3508 in a DCE or DTE configuration.
This Manual is split into sections to give the user the information necessary to perform a
thorough evaluation of the SP3508. The Board Schematic and Layout section describes
the I/O pins, the jumpers and the other components used on the evaluation board. The
board schematic, layout diagram and DB-25 connector are also covered in the Board
Schematic and Layout section. The Using the SP3508 Evaluation Board section details
the configuration of the SP3508 evaluation board for parametric testing.
Rev. 8/28/03
SP3508 Evaluation Board Manual
© Copyright 2003 Sipex Corporation
1
NOTES
1) Avoid parrallel traces on receiver inputs
Figure 1. SP3508 Schematic
Jumper
Figure 1
2) Add Test Point for VCC and GND for attachment of a power
supply.
3) Scope probe jack is Berg part # 33JR135-1
4) VDD (pin 76) and VSS1 (Pin 68) are to be routed as directly as possible to CVdd and CVss1 respectively.
Rev. 8/28/03
Jumper
Jumper
Config
GND
26
C1-1
2
24
C1+1
92
96
28
V
CC
0
26 048 09
88 999 12
57 4 15 0 48
1 24 5 77 8 88
C7 1uF
C3-
C3+
78
73
66
48
23
V
C3 1uF
1
+
+
CVss2 1uF
ST_B ST_A TT_B TT_A SD_B SD_A
CC
68
VSS1
Part Reference
GNDTP
C2+
C2-
VSS2
97
sda
27
VSS
69
C2-
72
C2+
CVss1 1uF
C2 1uF
1 2
Vss_2
2
P1-2
P1-14
TP33 TP34
TP31 TP32
14
24
11
15
P1-15
TP35 TP36
P1-12
P1-4
P1-19
TP39 TP40
TP37 TP38
12
4
19
20
23
TP41 TP42
P1-20
P1-23
P1-24
P1-11
CVdd
1uF
+
+
C1-
70
C1 1uF
+
C1+
74
C1-
C1+
Vdd
99
93
tta
ttb
sta
stb
rsa
rsb
tra
trb
rrca
rrcb
95
89
91
81
83
85
87
79
77
sdb
1
5) C1, C2, C3, CVdd, CVss1 and CVss2 footprint are size 1812 and are to be as close the the socket pins as
2
possible.
3
6) C7 is footprint 2220 and is to be placed where the power supply is attached
to the board.
Signal to be
7) Test points are MilMax part # 0300-1-15-01-4727100 0.040" round post.
accessed by DB25
8) JP1, JP2 ,JP3, JP4 and JP20 - JP41 are 3 pin 0.100" headers with
0.025" square post
STa
TxCa
9) JP5, JP9, JP50 and JP51 are 2 pin 0.100" headers with 0.25"
square post
STb
10) P1 is 25 pin male right angle D-SUB connector
TxCb
RRTa
11) SP3508 is a 100 pin LQFP
RRCa
12) R1 and R2 are 1/8 watt 50 ohm axial lead resistor
RRTb
13) U4 is Pomona Type 4788 BNC right angle female PC mount
RRCb
JP1
JP1
JP2
JP2
JP3
JP3
JP4
JP4
1-2
2-3
1-2
2-3
1-2
2-3
1-2
2-3
VDD
76
VDD
TP21
TxD
TXD
31
TxD
SD(a)
SD(b)
TP22
JP1
2
1 3
TT(a)
TxCE
TXCE
32
TxCE
TT(b)
TP23
JP2
2
1 3
JP50
2 1
ST
ST(a)
ST
33
ST
ST(b)
GND
AGND
RS(a)
TP24
RTS
RTS
34
RTS
RS(b)
V
CC
AV
CC
ttl
TP25
TR(a)
1
JP51
2
DTR
DTR
35
DTR
TR(b)
TTL
TP26
TP43 TP44
P1-1
TP45 TP46
RT_B RT_A RD_B RD_A
DCE_DCE
36
DCD_DCE
RRC(a)
DCE_DCE
RL(a)
67
rla
21
RRC(b)
1
P1-21
RL_A
R
R
C
_
B
T
R
_
B
T
R
_
A
P1-3
TP47 TP48
P1-16
P1-17
P1-9
TP51 TP52
TP49 TP50
3
16
R
R
C
_
A
R
S
_
B
R
S
_
A
LL(a)
65
lla
18
TP27
RL
RL
37
RL
R1 50Ω
BNC
P1-18 LL_A
2
1
RD(a)
50
rda
rdb
rta
rtb
txca
txcb
csa
csb
49
52
51
55
53
57
JP5
TP28
LL
LL
38
LL
R2
50Ω
RD(b)
RT(a)
RT(b)
TxC(a)
TxC(b)
CS(a)
RXD
39
RxD
JP31
JP29
JP27
JP28
JP30
JP32
JP33
JP26
JP34
JP35
JP36
JP37
JP38
JP39
JP40
JP41
SP3508 Evaluation Board Manual
17
9
P1-5
TP53 TP54
P1-13
P1-6
P1-22
P1-8
P1-10
TP57 TP58
TP55 TP56
CS(b)
DM(a)
dma
dmb
rrta
rrtb
59
58
62
61
56
2
5
13
6
22
JP3
2
1 3
JP4
2
1 3
8
10
IC_IN
ic
RXC
40
RxC
JP9
60
GNDV10
GND
JP52
Jumper
1 2 3
TXC
41
TxC
V
CC
4 AC INPUT
CTS
CTS
42
CTS
Description
DM(b)
RRT(a)
RRT(b)
IC
63
Jumper
Configuration
DSR
DSR
43
DSR
Input to GND
1-2
Input toV
CC
2-3
DCD_DTE
DCD_DTE
44
DCD_DTE
Input frin external
source
2-4
RI
D
M
_
B
25
P1-25
GND
D
M
_
A
C
S
_
B
C
S
_
A
RI
45
RI
V
TM(a)
64
TM_IN
CC
TM
TM_OUT
46
TM
R
R
T
_
B
R
R
T
_
A
Jumper
V
CC
1 2 3
Signal
JP20
123
V
CC
Signal
Term_off
JP21
12 3
T
M
_
a
Jumper
JP20
JP21
JP22
JP23
JP24
LATCH TERM_OFF
latch
termoff
21
22
/D_LATCH
TERM_OFF
/RDEN
/RTEN
/TxCEN
/CSEN
/DMEN
/RRTEN
/ICEN
TMEN
10
11
12
13
14
15
16
17
rden
rten
txcen
csen
dmen
rrten
icen
tmen
D1 D0
DECODER
MODE
D0
D1
1
1
1
0
1
0
1
1
0
0
1
1
0
0
1
0
0
0
1
1
1
D2
SHUTDOWN
V.35
/D_Latch
D0
D1
D2
3 3 3 3 3 3 3 3
2 2 2 2 2 2 2 2
1 1 1 1 1 1 1 1
GND
1-2
1-2
1-2
1-2
1-2
VCC
2-3
2-3
2-3
2-3
2-3
D2
D0
18
D1
19
20
LOOPBACK
30
JP22
D0
D1
D2
/LOOPBACK
123
V
CC
JP23
EIA-530
RS-232
EIA-530A
RS-449
X.21
JP24
V
1 23
12 3
JP25
CC
D2
LOOPBACK
SDE
TTE
STE
RSE
TRE
RRCE
RLEN
/LLEN
2
3
4
5
6
7
8
9
sden
tten
sten
rsen
tren
rrcen
rlen
llen
12 3
3 3 3 3 3 3 3 3
2 2 2 2 2 2 2 2
1 1 1 1 1 1 1 1
/Loopback
TMEN
/ICEN
/RRTEN
/DMEN
/CSEN
/TxCEN
/RTEN
/RDEN
/LLEN
RLEN
RRCEN
TREN
RSEN
STEN
TTEN
SDEN
JP25
JP26
JP27
JP28
JP29
JP30
JP31
JP32
JP33
JP34
JP35
JP36
JP37
JP38
JP39
JP40
JP41
1-2
1-2
1-2
1-2
1-2
1-2
1-2
1-2
1-2
1-2
1-2
1-2
1-2
1-2
1-2
1-2
1-2
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
© Copyright 2003 Sipex Corporation
SP508 EVALUATION BOARD
BOARD LAYOUT
1. The SP3508 Evaluation Board has been
designed to easily and conveniently provide
access to all inputs and outputs under test.
2. Figure 1 is a schematic of the evaluation
board. The schematic shows the location of
the driver and receiver access points as well
as the Jumpers, V
CC
, GND and the DB-25
Connector.
3. Figure 3 to Figure 6 shows the layout of
the SP3508 Evaluation Board.
4. I/O Pinouts
The SP3508 Evaluation Board has been
designed to easily and conveniently provide
access to all inputs and outputs to the device
under test. Each Driver has probe points for
the inputs and outputs. Each Receiver has
probe points for the inputs and outputs.
5. At the left of the board is a set of jumpers.
Each driver and receiver has its own indi-
vidual enable pin. This set of jumpers con-
trols the enabling and disabling of each
driver of receiver. Another set of jumpers is
to configure the 3 bit decoder, to enable/
disable loopback, to enable/disable latch
and to enable/disable term_off functions. In
addition, JP1 - JP4 allow the user to choose
which signals the user can access through
the DB-25 connector. JP5 allows the user to
set the driver input to GND, V
CC
or external
source.
6. Also located on the SP3508 evaluation
board are six 1uf charge pump capacitors, a
1µF bypass capacitor for V
CC
and two 50Ω
termination resistors.
7. 1 Pomona BNC female connector is
mounted on the board to provide input signal
for evaluation.
8. Figure 2 shows a RS-232 & EIA530 DB-
25 Connector.
9. Table 1 shows the pinout of the DB-25
connector used to connect to a communica-
tion analyzer such as the TTC Firebird 6000.
1
13
14
25
Figure 2. RS-232 & EIA530 Connector (ISO 2110), DTE
Connector
σ
DB-25 Male, DCE Connector
σ
DB-25
Female
Rev. 8/28/03
SP3508 Evaluation Board Manual
© Copyright 2003 Sipex Corporation
3
Transmitter
Outputs
Transmitter
and Receiver
Enable Pins
Receiver
Inputs
Receiver
Outputs
Transmitter
Inputs
Note: All six charge pump caps are located next to the DUT.
Control pins (D0,D1, D2), / LOOPBACK, / D_LATCH, and TERMOFF are also included.
Figure 3. SP3508 Evaluation Board Layout
Rev. 8/28/03
SP3508 Evaluation Board Manual
© Copyright 2003 Sipex Corporation
4
Figure 4. SP3508 Evaluation Board Ground Plane
Figure 5. SP3508 Evaluation Board V
CC
Plane
Rev. 8/28/03
SP3508 Evaluation Board Manual
© Copyright 2003 Sipex Corporation
5
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