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SP7545KCL

12-Bit, Buffered Multiplying DAC

器件类别:模拟混合信号IC    转换器   

厂商名称:SIPEX

厂商官网:http://www.sipex.com/

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器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
SIPEX
包装说明
PLASTIC, LCC-20
Reach Compliance Code
unknow
最大模拟输出电压
15.3 V
最小模拟输出电压
-0.3 V
转换器类型
D/A CONVERTER
输入位码
BINARY, OFFSET BINARY
输入格式
PARALLEL, WORD
JESD-30 代码
S-PQCC-J20
JESD-609代码
e0
长度
8.9535 mm
最大线性误差 (EL)
0.0244%
位数
12
功能数量
1
端子数量
20
最高工作温度
70 °C
最低工作温度
封装主体材料
PLASTIC/EPOXY
封装代码
QCCJ
封装等效代码
LDCC20,.4SQ
封装形状
SQUARE
封装形式
CHIP CARRIER
电源
5/15 V
认证状态
Not Qualified
座面最大高度
4.57 mm
最大稳定时间
2 µs
标称安定时间 (tstl)
2 µs
最大压摆率
2 mA
标称供电电压
5 V
表面贴装
YES
技术
CMOS
温度等级
COMMERCIAL
端子面层
Tin/Lead (Sn/Pb)
端子形式
J BEND
端子节距
1.27 mm
端子位置
QUAD
宽度
8.9535 mm
文档预览
SP7545
Corporation
SIGNAL PROCESSING EXCELLENCE
12–Bit, Buffered Multiplying DAC
s
±1.0
LSB Relative Accuracy Over
Temperature
s
Monotonic to 12–Bits Over
Temperature
s
High Stability, Segmented Architecture
s
Proprietary, Low TCR Thin–Film
Resistor Technology
s
Operates With +5V to +15V Power
Supplies
s
On-Board, Level–Triggered Latches
s
2kVESD Protection on all Digital
Inputs
DESCRIPTION…
The
SP7545
is a low–cost, high stability 12–bit CMOS multiplying DAC with on–board data
latches. The
SP7545
is constructed using a proprietary low–TCR thin–film process that
requires no laser–trimming to achieve 12–bit performance. With no laser–trimming, inherent
high stability, and a segmented (decoded) DAC architecture, the
SP7545
retains its
performance over time and temperature. The
SP7545
is available for use in commercial and
industrial temperature ranges. It is available in 20–pin plastic DIP and PLCC packages.
V
DD
[18]
D
11
(MSB) [4]
D
10
[5]
D
9
[6]
D
8
[7]
D
7
[8]
D
6
[9]
D
5
[10]
D
4
[11]
D
3
[12]
AGND [2]
D
2
[13]
D
1
[14]
D
0
(LSB) [15]
12–BIT
DAC
REGISTER
12–BIT
DAC
I
O1
[1]
R
FB
[20]
V
REF
[19]
GND [3]
Corporation
175
SIGNAL PROCESSING EXCELLENCE
ABSOLUTE MAXIMUM RATINGS
(T
A
= 25°C unless otherwise noted.)
These are stress ratings only and functional operation of the device
at these or any other above those indicated in the operation
sections of the specifications below is not implied. Exposure to
absolute maximum rating conditions for extended periods of time
may affect reliability.
V
DD
to GND .................................................................. –0.3V, +17V
Digital Input Voltage to GND ................................. –0.3V, V
DD
+0.3V
V
REF
or V
RFB
to GND ................................................................
±25V
Output Voltage (Pin 1, Pin 2) ................................ –0.3V, V
DD
+0.3V
Power Dissipation (Any Package to +75°C) ........................ 450mW
Derates above 75°C by ...................................................... 6mW/°C
Dice Junction Temperature ................................................. +150°C
Storage Temperature ............................................ –65°C to +150°C
Lead Temperature (Soldering, 60 seconds) ........................ +300°C
SPECIFICATIONS
(T
A
=25°C; V
DD
=+5V or +15V as noted; V
REF
= +10V; I
O1
= AGND = GND = 0V; unipolar unless otherwise noted.)
PARAMETER
STATIC PERFORMANCE
Resolution
Integral Non-Linearity
–J
–K
Differential Non-Linearity
–J
–K
Gain Error
–J
–K
MIN.
12
TYP.
MAX.
UNIT
Bits
CONDITIONS
±2.0
±1.0
±4.0
±1.0
±20
±25
±10
±15
±10
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
nA
Output Leakage Current
AC PERFORMANCE CHARACTERISTICS
Propagation Delay
Current Settling Time
Output Capacitance
50
25
Glitch Energy
Multiplying Feedthrough Error
STABILITY
Gain Error TC
Integral Non-Linearity TC
Differential Non-Linearity TC
Power Supply Rejection
250
2.0
0.2
±1.0
±0.1
±0.1
±0.002
300
250
2.0
200
200
70
70
ns
ns
µs
pF
pF
pF
pF
nV-s
mV
P-P
mV
P-P
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
%/%
%/%
KΩ
ppm/°C
Volts
Note 6
Note 5; 11-bit relative accuracy
Note 5; 12-bit relative accuracy
Note 7
Note 5; monotonic to 12-bits
Note 5; monotonic to 12-bits
Note 16
V
DD
= +5V; Note 5
V
DD
= +15V
V
DD
= +5V
V
DD
= +15V
At I
O1
(Pin 1); Note 5 and 17
Output Amplifier HOS-050;
Note 10
V
DD
= +5V; Note 11
V
DD
= +15V; Note 11
Full scale transition; Note 12
WR, CS = 0V; data inputs V
DD
Note 5; data inputs V
DD
Data inputs 0V
Note 5; data inputs 0V
Note 13
Measured at output I
O1
; Note 14
Measured at output I
O1
; Note 15
±2.0
±2.0
±1.0
±1.0
±1.0
±1.0
±0.01
±0.02
Note 5
Note 5
Note 5
%/0.005% change in power
supply voltage
Note 5
Pin 19 to GND
Note 5 and 8
REFERENCE INPUT
Input Resistance
Input Resistance TC
Voltage Range
7
10
±150
15
±25
176
Corporation
SIGNAL PROCESSING EXCELLENCE
SPECIFICATIONS
(continued)
(T
A
=25°C; V
DD
=+5V, V
REF
= +10V; I
O1
= AGND = GND = 0V; unipolar unless otherwise noted.)
PARAMETER
DIGITAL INPUTS
Logic Levels
V
IH
MIN.
TYP.
MAX.
UNIT
CONDITIONS
2.4
13.5
V
IL
-0.3
-0.3
Input Current
Input Capacitance
Bits 1—12
WR, CS
Coding
Unipolar
Bipolar
POWER REQUIREMENTS
Supply Current
V
DD
2.4
V
DD
13.5
0.8
0.8
1.5
1.5
±1.0
±10
5
20
Binary
Offset Binary
2.0
2.0
0.5
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
µA
µA
pF
pF
V
DD
= +5V
V
DD
= +5V; Note 5
V
DD
= +15V
V
DD
= +15V; Note 5
V
DD
= +5V
V
DD
= +5V; Note 5
V
DD
= +15V
V
DD
= +15V; Note 5
V
IN
= 0V or V
DD
Note 5 and 9
V
IN
= 0; Note 5 and 8
mA
mA
mA
mA
All digital inputs V
IL
or V
IH
Note 5; all digital inputs
V
IL
or V
IH
Note 18
Note 5 and 18
ENVIRONMENTAL AND MECHANICAL
Operating Temperature
Commercial
0
+70
Industrial
-40
+85
Storage Temperature
-65
+150
Package
20–pin Plastic DIP
20–pin Plastic LCC
°C
°C
°C
Notes and Cautions:
1.
Do not apply voltages higher than V
DD
or less than GND potential on any terminal other than V
REF
or V
RFB
.
2.
The digital inputs are diode-clamp protected against ESD damage. However, permanent damage may
occur on unprotected units from high-energy electrostatic fields. Keep units in conductive foam at all
times until ready to use.
3.
Use proper anti-static handling procedures.
4.
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation at or above these specifications is not
implied. Exposure to the above maximum rated conditions for extended periods may affect device
reliability.
5.
From T
MIN
to T
MAX
.
6.
End-point linearity
7.
Differential Non-linearity is the deviation of an output step from the theoretical value of 1 LSB for any two
adjacent digital input codes.
8.
Guaranteed by design, but not production tested.
9.
Logic inputs are MOS gates. I
IN
typically is less than 1nA @ 25°C.
10.
AC performance characteristics are included for design guidance only and are subject to sample testing
only.
11.
R
L
= 100Ω, C
EXT
= 13pF; all data inputs 0V to V
DD
or V
DD
to 0V; from 50% digital input change to 90% of
final analog output.
12.
Settling to
±0.01%
FSR (strobed); all data inputs 0V to V
DD
or V
DD
to 0V.
13.
V
REF
= 0V, DAC register alternatively loaded with all 0’s and all 1’s.
14.
V
REF
= 20V
P-P
; F = 10kHz sinewave.
15.
V
REF
= 20V
P-P
; F = 1kHz sinewave.
16.
Measured using internal feedback resistor with DAC loaded with all 1’s.
17.
All digital inputs = 0V.
18.
All digital inputs 0V or V
DD.
Corporation
177
SIGNAL PROCESSING EXCELLENCE
ORDERING INFORMATION
Model
Integral Linearity
Package
0°C to +70°C Operating Temperature
SP7545JCN
............................................................................
±2LSB
.................................................................................. 20–pin, 0.3" Plastic DIP
SP7545JCL
.............................................................................
±2LSB
................................................................................................... 20–pin PLCC
SP7545KCN
............................................................................
±1LSB
.................................................................................. 20–pin, 0.3" Plastic DIP
SP7545KCL
............................................................................
±1LSB
................................................................................................... 20–pin PLCC
–40°C to +85°C Operating Temperature
SP7545JIN
..............................................................................
SP7545JIL
..............................................................................
SP7545KIN
.............................................................................
SP7545KIL
..............................................................................
±2LSB
±2LSB
±1LSB
±1LSB
.................................................................................. 20–pin, 0.3" Plastic DIP
................................................................................................... 20–pin PLCC
.................................................................................. 20–pin, 0.3" Plastic DIP
................................................................................................... 20–pin PLCC
180
Corporation
SIGNAL PROCESSING EXCELLENCE
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参数对比
与SP7545KCL相近的元器件有:SP7545、SP7545JCN、SP7545KCN、SP7545JCL、SP7545KIL、SP7545KIN、SP7545JIL、SP7545JIN。描述及对比如下:
型号 SP7545KCL SP7545 SP7545JCN SP7545KCN SP7545JCL SP7545KIL SP7545KIN SP7545JIL SP7545JIN
描述 12-Bit, Buffered Multiplying DAC 12-Bit, Buffered Multiplying DAC 12-Bit, Buffered Multiplying DAC 12-Bit, Buffered Multiplying DAC 12-Bit, Buffered Multiplying DAC 12-Bit, Buffered Multiplying DAC 12-Bit, Buffered Multiplying DAC 12-Bit, Buffered Multiplying DAC 12-Bit, Buffered Multiplying DAC
是否Rohs认证 不符合 - 不符合 不符合 不符合 不符合 不符合 不符合 不符合
厂商名称 SIPEX - SIPEX - SIPEX SIPEX - SIPEX -
包装说明 PLASTIC, LCC-20 - 0.300 INCH, PLASTIC, DIP-20 0.300 INCH, PLASTIC, DIP-20 PLASTIC, LCC-20 PLASTIC, LCC-20 0.300 INCH, PLASTIC, DIP-20 PLASTIC, LCC-20 0.300 INCH, PLASTIC, DIP-20
Reach Compliance Code unknow - unknow unknow unknow unknow unknow unknow unknow
最大模拟输出电压 15.3 V - 15.3 V 15.3 V 15.3 V 15.3 V - 15.3 V -
最小模拟输出电压 -0.3 V - -0.3 V -0.3 V -0.3 V -0.3 V - -0.3 V -
转换器类型 D/A CONVERTER - D/A CONVERTER D/A CONVERTER D/A CONVERTER D/A CONVERTER D/A CONVERTER D/A CONVERTER D/A CONVERTER
输入位码 BINARY, OFFSET BINARY - BINARY, OFFSET BINARY BINARY, OFFSET BINARY BINARY, OFFSET BINARY BINARY, OFFSET BINARY BINARY, OFFSET BINARY BINARY, OFFSET BINARY BINARY, OFFSET BINARY
输入格式 PARALLEL, WORD - PARALLEL, WORD PARALLEL, WORD PARALLEL, WORD PARALLEL, WORD PARALLEL, WORD PARALLEL, WORD PARALLEL, WORD
JESD-30 代码 S-PQCC-J20 - R-PDIP-T20 R-PDIP-T20 S-PQCC-J20 S-PQCC-J20 R-PDIP-T20 S-PQCC-J20 R-PDIP-T20
JESD-609代码 e0 - e0 e0 e0 e0 e0 e0 e0
长度 8.9535 mm - 25.908 mm 25.908 mm 8.9535 mm 8.9535 mm 25.908 mm 8.9535 mm 25.908 mm
最大线性误差 (EL) 0.0244% - 0.0488% 0.0244% 0.0488% 0.0244% 0.0244% 0.0488% 0.0488%
位数 12 - 12 12 12 12 12 12 12
功能数量 1 - 1 1 1 1 1 1 1
端子数量 20 - 20 20 20 20 20 20 20
最高工作温度 70 °C - 70 °C 70 °C 70 °C 85 °C 85 °C 85 °C 85 °C
封装主体材料 PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 QCCJ - DIP DIP QCCJ QCCJ DIP QCCJ DIP
封装等效代码 LDCC20,.4SQ - DIP20,.3 DIP20,.3 LDCC20,.4SQ LDCC20,.4SQ DIP20,.3 LDCC20,.4SQ DIP20,.3
封装形状 SQUARE - RECTANGULAR RECTANGULAR SQUARE SQUARE RECTANGULAR SQUARE RECTANGULAR
封装形式 CHIP CARRIER - IN-LINE IN-LINE CHIP CARRIER CHIP CARRIER IN-LINE CHIP CARRIER IN-LINE
电源 5/15 V - 5/15 V 5/15 V 5/15 V 5/15 V 5/15 V 5/15 V 5/15 V
认证状态 Not Qualified - Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
座面最大高度 4.57 mm - 5.334 mm 5.334 mm 4.57 mm 4.57 mm 5.334 mm 4.57 mm 5.334 mm
最大稳定时间 2 µs - 2 µs 2 µs 2 µs 2 µs 2 µs 2 µs 2 µs
标称安定时间 (tstl) 2 µs - 2 µs 2 µs 2 µs 2 µs 2 µs 2 µs 2 µs
最大压摆率 2 mA - 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA
标称供电电压 5 V - 5 V 5 V 5 V 5 V 5 V 5 V 5 V
表面贴装 YES - NO NO YES YES NO YES NO
技术 CMOS - CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 COMMERCIAL - COMMERCIAL COMMERCIAL COMMERCIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
端子面层 Tin/Lead (Sn/Pb) - Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
端子形式 J BEND - THROUGH-HOLE THROUGH-HOLE J BEND J BEND THROUGH-HOLE J BEND THROUGH-HOLE
端子节距 1.27 mm - 2.54 mm 2.54 mm 1.27 mm 1.27 mm 2.54 mm 1.27 mm 2.54 mm
端子位置 QUAD - DUAL DUAL QUAD QUAD DUAL QUAD DUAL
宽度 8.9535 mm - 7.62 mm 7.62 mm 8.9535 mm 8.9535 mm 7.62 mm 8.9535 mm 7.62 mm
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