SPT9687
DUAL ULTRAFAST VOLTAGE COMPARATOR
FEATURES
•
•
•
•
•
•
Propagation Delay <2.3 ns
Propagation Delay Skew <300 ps
Low Power: 185 mW
Low Offset
±3
mV
Low Feedthrough and Crosstalk
Differential Latch Control
APPLICATIONS
•
•
•
•
•
•
High-Speed Instrumentation, ATE
High-Speed Timing
Window Comparators
Line Receivers
A/D Conversion
Threshold Detection
GENERAL DESCRIPTION
The SPT9687 is a dual, very high-speed monolithic com-
parator. It is pin compatible with, and has improved perfor-
mance over Analog Device's AD9687. The SPT9687 is
designed for use in Automatic Test Equipment (ATE), high-
speed instrumentation, and other high-speed comparator
applications.
Improvements over other sources include reduced power
consumption, reduced propagation delays, and higher input
impedance.
The SPT9687 is available in 16-lead SOIC, 16-lead plastic
DIP, 20-lead PLCC and 20-contact LCC packages over the
industrial temperature range. It is also available in die form.
BLOCK DIAGRAM
Inverting Input
Latch Enable
-
+
Noninverting Input
Latch Enable
A
Q Output
VEE
VCC
GNDA
Q Output
Q Output
GNDB
Q Output
B
-
Latch Enable
Inverting Input
B
+
Latch Enable
Noninverting Input
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: (719) 528-2300 FAX: (719) 528-2370 Website: http://www.spt.com E-Mail: sales@spt.com
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)
1
25
°
C
Supply Voltages
Positive Supply (V
CC
to GND) .................. -0.5 to +6.0 V
Negative Supply (V
EE
to GND) ................ -6.0 to +0.5 V
Ground Voltage Differential ...................... -0.5 to +0.5 V
Input Voltages
Input Voltage ............................................ -4.0 to +4.0 V
Differential Input Voltage .......................... -5.0 to +5.0 V
Input Voltage, Latch Controls ..................... V
EE
to 0.5 V
Note:
Output
Output Current ...................................................... 30 mA
Temperature
Operating Temperature, ambient .............. -25 to +85
°C
junction ....................... +150
°C
Lead Temperature, (soldering 60 seconds) ...... +300
°C
Storage Temperature .............................. -65 to +150
°C
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
T
A
= +25
°C,
V
CC
= +5.0 V, V
EE
= -5.20 V, R
L
= 50 Ohm, unless otherwise specified.
PARAMETERS
Input Offset Voltage
Input Offset Voltage
Offset Voltage Tempco
Input Bias Current
Input Bias Current
Input Offset Current
Input Offset Current
Input Common Mode Range
Latch Enable
Common Mode Range
Open Loop Gain
Input Resistance
Input Capacitance
Input Capacitance
Power Supply Sensitivity
Common Mode Rejection Ratio
Positive Supply Current
Negative Supply Current
Positive Supply Voltage
Negative Supply Voltage
Power Dissipation
Output High
Output Low
TEST
CONDITIONS
R
S
= 0 Ohms
1
R
S
= 0 Ohms
1
T
MIN
<T
A
<T
MAX
TEST
LEVEL
III
IV
V
I
MIN
-3
-3.5
SPT9687
TYP
±.5
MAX
+3
+3.5
UNITS
mV
mV
µV/°C
µA
µA
µA
µA
V
V
V/V
kΩ
pF
pF
dB
dB
DC ELECTRICAL CHARACTERISTICS
4
6
7
-1.0
-1.5
-2.5
-2.0
4000
60
3
1
50
50
100
85
7
27
4.75
-4.95
5.0
-5.2
185
-.98
-1.95
11
37
5.25
-5.45
250
-.81
-1.63
±20
±38
+1.0
+1.5
+2.5
0
T
MIN
<T
A
<T
MAX
T
MIN
<T
A
<T
MAX
IV
I
IV
I
IV
V
V
V
(LCC Package)
V
CC
and V
EE
V
IV
IV
I
I
IV
IV
mA
mA
V
V
mW
V
V
I
OUTPUT
= 0 mA
50 Ohms to -2 V
50 Ohms to -2 V
I
I
I
OUTPUT LOGIC LEVELS (ECL 10 KH Compatible)
AC ELECTRICAL CHARACTERISTICS
2
Propagation Delay
Latch Set-up Time
10 mV OD
III
IV
2.0
0.6
2.3
1
ns
ns
SPT
SPT9687
2
3/21/97
ELECTRICAL SPECIFICATIONS
T
A
= +25
°C,
V
CC
= +5.0 V, V
EE
= -5.20 V, R
L
= 50 Ohm, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
MIN
SPT9687
TYP
MAX
UNITS
AC ELECTRICAL CHARACTERISTICS
2
Latch to Output Delay
Latch Pulse Width
Latch Hold Time
Rise Time
Fall Time
1
R
S
= Source impedance.
2
100 mV input step.
50 mV OD
IV
V
IV
2
3
ns
ns
0.5
1.2
1.2
ns
ns
ns
20% to 80%
20% to 80%
V
V
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
Unless otherwise noted, all tests are pulsed
tests; therefore, T
J
= T
C
= T
A
.
Figure 1 - Timing Diagram
LATCH ENABLE
TEST LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at T
A
=25
°C,
and sample
tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design
and characterization data.
Parameter is a typical value for information purposes
only.
100% production tested at T
A
= 25
°C.
Parameter is
guaranteed over specified temperature range.
50%
LATCH ENABLE
t
S
DIFFERENTIAL
INPUT VOLTAGE
V
OD
t
pdL
OUTPUT Q
50%
t
pLOH
t
H
tpL
VREF ± VOS
50%
OUTPUT Q
t
pdH
t
pLOL
V
IN
+ = 100 mV (p-p), V
OD
= 50 mV
The set-up and hold times are a measure of the time required for an input signal to propagate through the
first stage of the comparator to reach the latching circuitry. Input signals occurring before t
s
will be detected
and held; those occurring after t
H
will not be detected. Changes between t
s
and t
H
may not be detected.
SPT
SPT9687
3
3/21/97
SWITCHING TERMS (Refer to figure 1)
t
pdH
INPUT TO OUTPUT HIGH DELAY - The propagation
delay measured from the time the input signal
crosses the reference voltage (± the input offset
voltage) to the 50% point of an output LOW to HIGH
transition.
INPUT TO OUTPUT LOW DELAY - The propagation
delay measured from the time the input signal crosses
the reference voltage (± the input offset voltage) to the
50% point of an output HIGH to LOW transition.
GENERAL INFORMATION
The SPT9687 is an ultrahigh-speed dual voltage compara-
tor. It offers tight absolute characteristics. The device has
differential analog inputs and complementary logic outputs
compatible with ECL systems. The output stage is adequate
for driving terminated 50 ohm transmission lines.
The SPT9687 has a complementary latch enable control for
each comparator. Both should be driven by standard ECL logic
levels.
The dual comparator shares the same V
CC
and V
EE
connec-
tions but have separate grounds for each comparator to
achieve high crosstalk rejection.
Figure 2 - Internal Functional Diagram
t
pdL
t
pLOH
LATCH ENABLE TO OUTPUT HIGH DELAY - The
propagation delay measured from the 50% point of
the Latch Enable signal LOW to HIGH transition to
50% point of an output LOW to HIGH transition.
V
OD
VOLTAGE OVERDRIVE - The difference between
the differential input and the reference voltages.
Q
V
IN
+
-
t
pLOL
LATCH ENABLE TO OUTPUT LOW DELAY - The
propagation delay measured from the 50% point of
the Latch Enable signal LOW to HIGH transition to the
50% point of an output HIGH to LOW transition.
t
H
MINIMUM HOLD TIME - The minimum time after the
negative transition of the Latch Enable signal that the
input signal must remain unchanged in order to be
acquired and held at the outputs.
MINIMUM LATCH ENABLE PULSE WIDTH - The
minimum time that the Latch Enable signal must be
HIGH in order to acquire an input signal change.
MINIMUM SET-UP TIME - The minimum time before
the negative transition of the Latch Enable signal that
an input signal change must be present in order to be
acquired and held at the outputs.
PRE
AMP
LATCH
ECL
OUT
V
IN
Q
REF
1
REF
2
CLK
BUF
V
EE
V
CC
GND1
LE
LE
GND2
TYPICAL INTERFACE CIRCUIT
The typical interface circuit using the comparator is shown
in figure 3. Although it needs few external components
and is easy to apply, there are several conditions that
should be met to achieve optimal performance. The very
high operating speeds of the comparator require careful
layout, decoupling of supplies, and proper design of trans-
mission lines.
Since the SPT9687 comparator is a very high frequency and
high gain device, certain layout rules must be followed to
avoid spurious oscillations. The comparator should be sol-
dered to the board with component lead lengths kept as short
as possible. A ground plane should be used, and the input
impedance to the part should be kept as low as possible to
decrease parasitic feedback. If the output board traces are
longer than approximately one-half inch, microstripline tech-
niques must be employed to prevent ringing on the output
waveform. Also, the microstriplines must be terminated at
the far end with the characteristic impedance of the line to
prevent reflections. All supply voltage pins should be de-
coupled with high frequency capacitors as close to the
device as possible. All ground and N/C pins should be
connected to the same ground plane to further improve noise
immunity and shielding. If using the SPT9687 as a single
comparator, the outputs of the inactive comparator can be
grounded, left open or terminated with 50 Ohms to -2 V. All
outputs on the active comparator, whether used or unused,
should have identical terminations to minimize ground cur-
rent switching transients.
Note: To ensure proper power up of the device, the input
should be kept below +1.5 V during power up.
t
pL
t
S
TIMING INFORMATION
The timing diagram for the comparator is shown in figure 1.
The latch enable (LE) pulse is shown at the top. If LE is high
and LE low in the SPT9687, the comparator tracks the
input difference voltage. When LE is driven low and LE
high, the comparator outputs are latched into their existing
logic states.
The leading edge of the input signal (which consists of a
50 mV overdrive voltage) changes the comparator output
after a time of t
pdL
or t
pdH
(Q or Q ). The input signal must be
maintained for a time t
s
(set-up time) before the LE falling
edge and LE rising edge and held for time t
H
after the falling
edge for the comparator to accept data. After t
H
, the output
ignores the input status until the latch is strobed again. A
minimum latch pulse width of t
pL
is needed for strobe
operation, and the output transitions occur after a time of
t
pLOH
or t
pLOL
.
SPT
SPT9687
4
3/21/97
Figure 3 - Typical Interface Circuit
Figure 4 - Typical Interface With Hysteresis
VCC GND VEE
VO
VCC
GND
VEE
.1 µF
VIN
.1 µF
VIN
VREF
Noninverting
Input
+
-
Inverting
Input
Q OUTPUT
Q OUTPUT
VIN
VRef
Noninverting
Input
+
Inverting
Input
Q Output
Q Output
LE
LE
RL
50
Ω
RL
50
Ω
.1 µF
-
RL
50
Ω
LE
LE
-2 V
RL
50
Ω
-2 V
300
Ω
VLE
VLE
300
Ω
-5.2 V
-5.2 V
.1 µF
100
Ω
0.1 µF
100
Ω
ECL
= Represents line termination.
Hysteresis is obtained by applying a DC bias to the LE pin.
V
LE
= -1.3 V ±100 mV, V
LE
= -1.3 V.
Represents line termination.
Figure 5 - Equivalent Input Circuit
Figure 6 - AC Test Fixture
V +
IN
MONITOR
V
CC
(+5.0 V)
GND
VCC
15 µF
L1
6
SEMI
RIGID
Q3
L3
R
C
1
R 2
Q9
6
V +
IN
0.1 µF
50
50
L2
6
SEMI
RIGID
V
6
SEMI
RIGID
+
IN
1 pF
IN
1 pF
Q11
C
SEMI-
RIGID
6
100
SEMI-
RIGID
+
V+
Q
Q
100
0.1 µF
100
50
OUT
V -
IN
DUT
4
-
LE
LE
V-
V
OUT
-
R
V
IN
IN
Q1
Q
Q4
Q5
7
50
0.1 µF
100
Ω
V
L2
PRE
100
100
0.1 µF
50
SAMPLING
SCOPE
R
VIN
IN
V
PRE
100
Ω
V
R2
L1
50
50
L1
SEMI
RIGID
SEMI
RIGID
VR1
Q2
Q6
Q8
Q
10
Q
12
SEMI
RIGID
6
SEMI
RIGID
6
6
6
15 µF
15 µF
TANT
-
+
+
-
R3
V
EE
R4
R5
R6
R7
LE
MONITOR
LE
LE
LE
MONITOR
V
EE
(-5.2 V)
V
pD
(-4.0 V)
Figure 7 - Output Circuit
R7
240
Ω
R8
240
Ω
Figure 8 - Test Load
Rz
50
Ω
Coax
50
Ω
Q24
Q23
RL
Q Output
V1
Q21
Q22
V2
Q Output
RZ
100
Ω
100
Ω
4.5 mA
Vpd
(-4.0 V)
SPT
SPT9687
5
3/21/97
