PF805-04
SRM20V100LLMX
7
SRM20V100LLMX
7
1M-Bit Static RAM
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lta
Vo n
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Lo pe ct
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DESCRIPTION
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Low Supply Voltage
q
Wide Temperature Range
q
Low Supply Current
q
Access Time 70ns (2.7V)
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131,072 Words×8-Bit Asynchronous
The SRM20V100LLMX
7
is an 131,072 words×8-bit asynchronous, static, random access memory on a monolithic
CMOS chip. Its very low standby power requirement makes it ideal for applications requiring non-volatile storage
with back-up batteries. And —25 to 85°C operating temperature range makes it ideal for portable equipment.
The asynchronous and static nature of the memory requires no external clock or refreshing circuit. Both the
input and output ports are TTL compatible and 3-state output allows easy expansion of memory capacity.
s
FEATURES
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Wide temperature range ..... –25 to 85°C
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Fast Access time ................. SRM20V100LLMX
7
70ns (Max.)
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Low supply current .............. standby: 0.6µA (Typ.): LL Version
0.3µA (Typ.): SL Version
operation: 8mA/1MHz (Typ.)
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Completely static ................. No clock required
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Supply voltage..................... 2.7V to 3.6V
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TTL compatible inputs and outputs
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3-state output with wired-OR capability
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Non-volatile storage with back-up batteries
SOP6-32pin (plastic)
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Package ...... SRM20V100LLMX
7
SRM20V100LLTX
7
TSOP (
I
)-32pin (plastic)
SRM20V100LLRX
7
TSOP (
I
)-32pin-R1 (plastic)
SRM20V100LLKX
7
Slim-TSOP (
I
)-32pin (plastic)
SRM20V100LLYX
7
Slim-TSOP (
I
)-32pin-R1 (plastic)
s
PIN CONFIGURATION
(SOP6)
N.C.
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/01
I/02
I/03
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/08
I/07
I/06
I/05
I/04
SRM20V100LLMT
(TSOP/Slim-TSOP)
A11
A9
A8
A13
WE
CS2
A15
V
DD
N.C.
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/08
I/07
I/06
I/05
I/04
V
SS
I/03
I/02
I/01
A0
A1
A2
A3
SRM20V100LLTX/KX
s
BLOCK DIAGRAM
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
CS1
CS2
10
X Decoder
(TSOP-R1/Slim-TSOP-R1)
1024
Memory Cell Array
1024×128×8
128×8
7
128
Column Gate
A4
A5
A6
A7
A12
A14
A16
N.C.
V
DD
A15
CS2
WE
A13
A8
A9
A11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SRM20V100LLRX/YX
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A3
A2
A1
A0
I/01
I/02
I/03
V
SS
I/04
I/05
I/06
I/07
I/08
CS1
A10
OE
Address Buffer
Y
Decoder
CS1, CS2
Chip
Control
8
¡PIN
DESCRIPTION
A0 to A16 Address Input
WE
Write Enable
OE
Output Enable
CS1, CS2 Chip Select
I/O1 to I/O8 Data I/O
V
DD
Power Supply (2.7V to 3.6V)
V
SS
Power Supply (0V)
N. C.
No connection
OE
WE
OE, WE
Chip
Control
I/O Buffer
I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8
1
s
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply voltage
Input voltage
Input/Output voltage
Power dissipation
Operating temperature
Storage temperature
Soldering temperature and time
T
VI,
(V
SS
= 0V)
Ratings
–0.5 to 4.6
–0.5 to V
DD
+0.3
–0.5 to V
DD
+0.3
0.5
–25 to 85
–65 to 150
260°C, 10s (at lead)
Symbol
V
DD
V
I
V
I/O
P
D
T
opr
T
stg
T
sol
Unit
V
V
V
W
°C
°C
—
VI/O (Min.) = –3.0V (Pulse width is 50ns)
s
DC RECOMMENDED OPERATING CONDITIONS
Parameter
Supply voltage
Input voltage
T
If
Symbol
V
DD
V
SS
V
IH
V
IL
Conditions
—
—
—
—
Min.
2.7
0
2.2
–0.3
T
(V
SS
= 0V, Ta = –25 to 85°C)
Typ.
Max.
Unit
V
3.0
3.6
V
0
0
V
—
V
DD
+0.3
0.4
V
—
pulse width is less than 50ns, it is –3.0V
s
ELECTRICAL CHARACTERISTICS
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DC Electrical Characteristics
Parameter
Input leakage
Output leakage
Symbol
I
LI
I
LO
I
DDS
Standby supply current
I
DDS1
I
DDA
Average operating current
I
DDA1
Operating supply current
High level output voltage
Low level output voltage
I
DDO
V
OH
V
OL
Conditions
V
I
=0 to V
DD
CS1 = V
IH
or CS2 = V
IL
or WE = V
IL
or OE = V
IH
, V
IO
= 0 to V
DD
CS1 = V
IH
or CS2 = V
IL
CS1 = CS2≥V
DD
—0.2V
or CS2≤0.2V
V
I
= V
IL
, V
IH
I
I/O
= 0mA, t
cyc
= Min.
V
I
= V
IL
, V
IH
I
I/O
= 0mA, t
cyc
= 1µs
V
I
= V
IL
, V
IH
I
I/O
= 0mA
V
DD
≥3V,
I
OH
= –2.0mA
I
OH
= –100µA
V
DD
≥3V,
I
OL
= –2.0mA
I
OL
= 100µA
DD
=3.0V
(V
DD
= 2.7 to 3.6V, V
SS
= 0V, Ta = –25 to 85°C)
Min.
–1
–1
—
LL
SL
—
—
—
—
—
2.4
V
DD
—0.2
—
—
Typ.T
—
—
—
0.6
0.3
20
8
8
—
—
—
—
Max.
1
1
1.0
60
30
35
15
15
—
—
0.4
0.2
Unit
µA
µA
mA
µA
mA
mA
mA
V
V
T
Typical values are measured at Ta=25°C and V
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Terminal Capacitance
Parameter
Address Capacitance
Input Capacitance
I/O Capacitance
Symbol
C
ADD
C
I
C
I/O
Conditions
V
ADD
=0V
V
I
=0V
V
I/O
=0V
Min.
—
—
—
Typ.
—
—
—
(f = 1MHz, Ta = 25°C)
Max.
8
8
10
Unit
pF
pF
pF
2
SRM20V100LLMX
7
q
AC Electrical Characteristics
r
Read Cycle
Parameter
Read cycle time
Address access time
Chip select1 access time
Chip select2 access time
Output enable access time
Chip select1 output set time
Chip select1 output floating
Chip select2 output set time
Chip select2 output floating
Output enable output set time
Output enable output floating
Output hold time
Symbol
t
RC
t
ACC
t
ACS1
t
ACS2
t
OE
t
CLZ1
t
CHZ1
t
CLZ2
t
CHZ2
t
OLZ
t
OHZ
t
OH
Conditions
(V
DD
= 2.7V to 3.6V, V
SS
= 0V, Ta = –25 to 85°C)
Min.
70
—
—
—
—
5
—
5
—
0
—
10
Max.
—
70
70
70
40
—
30
—
30
—
30
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T1
T2
T1
r
Write Cycle
Parameter
Write cycle time
Chip select time1
Chip select time2
Address enable time
Address setup time
Write pulse width
Address hold time
Input data setup time
Input data hold time
WE Output floating
WE Output setup time
T
(V
DD
= 2.7V to 3.6V, V
SS
= 0V, Ta = –25 to 85°C)
Symbol
t
WC
t
CW1
t
CW2
t
AW
t
AS
t
WP
t
WR
t
DW
t
DH
t
WHZ
t
OW
Conditions
Min.
70
60
60
60
0
55
0
30
0
—
5
T
T1
T2
Max.
—
—
—
—
—
—
—
—
—
30
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
+3V
1 Test Conditions
1. Input pulse level: 0.4V to 2.4V
2. t
r
= t
f
= 5ns
3. Input and output timing reference
levels : 1.5V
4. Output load C
L
= 100pF
I/O
C
L
+3V
2 Test Conditions
1. Input pulse level : 0.4V to 2.4V
2. t
r
= t
f
= 5ns
3. Input timing reference levels: 1.5V
4. Output timing reference levels:
I/O
C
L
1.0kΩ
1.0kΩ
920Ω
±200mV
(the level displaced from
stable output voltage level)
5. Output load C
L
= 5pF
920Ω
C
L
=100pF (Includes Jig Capacitance)
C
L
=5pF (Includes Jig Capacitance)
3
q
Timing chart
rRead
Cylcle
T1
Address
t
ACC
t
ACS1
CS1
t
CLZ1
t
ACS2
CS2
t
CLZ2
t
OE
t
OLZ
Dout
t
OHZ
t
CHZ1
t
CHZ2
WE
t
CLZ1
Dout
t
DW
Din
t
DH
t
OH
Address
CS1
CS2
t
WR
t
WHZ
t
AS
t
AW
t
CW1
t
WR
t
RC
rWrite
Cycle (1) (CS1 Control)
T2
t
WC
OE
rWrite
Cycle (2) (CS2 Control)
T2
t
WC
Address
t
AW
t
CW2
CS1
t
AS
CS2
WE
t
WHZ
Dout
t
CLZ2
Din
t
DW
t
DH
t
WP
t
WR
rWrite
Cycle (3) (WE Control)
T3, T4
t
WC
Address
t
AW
CS1
t
AS
CS2
t
WP
WE
t
WHZ
Dout
Din
t
DW
t
OW
t
DH
t
WR
Note : 1. During read cycle time, WE is to be "H" level.
2. During write cycle time that is controlled by CS1 or CS2, Output Buffer is in high impedance state, whether OE level is "H" or "L".
3. During write cycle time that is controlled by WE, Output Buffer is high impedance state if OE is "H" level.
4. When I/O terminals are output mode, be careful that do not give the opposite signals to the I/O terminals.
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DATA RETENTION CHARACTERISTIC WITH LOW VOLTAGE POWER SUPPLY
(V
SS
= 0V, Ta = –25 to 85°C)
Parameter
Data retention Supply voltage
Data retention current
Chip select data hold time
Operation recovery time
T
Ta
Symbol
V
DDR
I
DDR
t
CDR
t
R
Conditions
Min.
2.0
Typ.
—
0.5
T
0.25
T
—
—
Max.
3.6
50
Unit
V
µA
V
DD
= 2.7V
CS1 = CS2≥V
DD
—0.2V
or CS2≤0.2V
LL
SL
—
—
0
5
25
—
—
ns
ms
= 25°C
Data retention timing
V
DD
t
CDR
CS1
2.7V
(CS1 Control)
2.7V
t
R
CS1≥V
DD
—0.2V
Data retention timing
V
DD
t
CDR
2.7V
(CS2 Control)
2.7V
t
R
Data hold mode
V
DDR
≥2.0V
Data hold mode
V
DDR≥
2.0V
V
IH
V
IH
CS2
V
IL
CS2≥0.2V
V
IL
T
when retaining data in standby mode, supply voltage can be lowered with in a certain range. But read or write cycle
cannot be performed while the supply voltage is low.
4
SRM20V100LLMX
7
s
FUNCTIONS
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Truth Table
CS1
H
X
L
L
L
X : "H" or "L"
CS2
X
L
H
H
H
OE
X
X
X
L
H
WE
X
X
L
H
H
DATA I/O
Hi-Z
Hi-Z
Input data
Output data
Hi-Z
Mode
Unselected
Unselected
Write
Read
Output disable
I
DD
I
DDS,
I
DDS1
I
DDS,
I
DDS1
I
DDO
I
DDO
I
DDO
q
Reading data
Data is able to be read when the address is set while holding CS1 = "L", CS2 = "H", OE = "L" and WE = "H".
Since DATA I/O terminals are in high impedance state when OE = "H", the data bus line can be used for any
other objective, then access time apparently is able to be cut down.
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Writing data
There are the following four ways of writing data into the memory.
(1) Hold CS2 = "H", WE = "L", set addresses and give "L" pulse to CS1.
(2) Hold CS1 = "L", WE = "L" ,set addresses and give "H"pulse to CS2.
(3) Hold CS1 = "L", CS2 = "H", set addresses and give "L" pulse to WE.
(4) After setting addresses, give "L" pulse to CS1, WE and give "H" pulse to CS2.
Anyway, data on the Data I/O terminals are latched up into the SRM20V100LLMX
7
at the end of the period that
CS1, WE are "L" level, and CS2 is "H" level. As Data I/O terminals are in high impedance state when any of
CS1, OE = "H", or CS2 = "L", the contention on the data bus can be avoided.
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Standby mode
When CS1 is "H" or CS2 is "L" level, the SRM20V100LLMX
7
is in the standby mode which has retaining data
operation. In this case Data I/O terminals are Hi-Z, and all inputs of addresses, WE and data can be any "H" or
"L". When CS1 and CS2 level are in the range over V
DD
-0.2V, CS2 level is in the range under 0.2V, in the
SRM20V100LLMX
7
there is almost no current flow except through the high resistance parts of the memory.
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