Integrated
Circuit
Systems, Inc.
ICSSSTV16859
DDR 13-Bit to 26-Bit Registered Buffer
Recommended Applications:
• DDR Memory Modules
• Provides complete DDR DIMM logic solution with
ICS93V857 or ICS95V857
• SSTL_2 compatible data registers
Product Features:
• Differential clock signals
• Meets SSTL_2 signal data
• Supports SSTL_2 class II specifications on outputs
• Low-voltage operation
- V
DD
= 2.3V to 2.7V
• Available in 64 pin TSSOP and 56 pin VFQFN (MLF2)
packages
Pin Configurations
Q13A
Q12A
Q11A
Q10A
Q9A
VDDQ
GND
Q8A
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
GND
Q1A
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
Q8B
Q7B
Q6B
GND
VDDQ
Q5B
Q4B
Q3B
Q2B
Q1B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDQ
GND
D13
D12
VDD
VDDQ
GND
D11
D10
D9
GND
D8
D7
RESET#
GND
CLK#
CLK
VDDQ
VDD
VREF
D6
GND
D5
D4
D3
GND
VDDQ
VDD
D2
D1
GND
VDDQ
Truth Table
1
Inputs
RESET#
L
H
H
H
CLK
X or
Floating
-
-
L or H
CLK#
X or
Floating
¯
¯
L or H
D
X or
Floating
H
L
X
Q Outputs
Q
L
H
L
Q
0(2)
64-Pin TSSOP
6.10 mm. Body, 0.50 mm. pitch
Q8A
VDDQ
Q9A
Q10A
Q11A
Q12A
Q13A
VDDQ
GND
D13
D12
VDD
VDDQ
D11
56
43
Notes:
1.
H = "High" Signal Level
L = "Low" Signal Level
↑
= Transition "Low"-to-"High"
↓
= Transition "High"-to-"Low"
X = Don't Care
Output level before the indicated steady state
input conditions were established.
2.
Block Diagram
CLK
CLK#
RESET#
D1
VREF
R
CLK
D1
Q1A
Q1B
Q7A
1
Q6A
Q5A
Q4A
Q3A
Q2A
Q1A
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
Q8B
14
15
ICSSSTV16859
42
D10
ICSSSTV16859
D9
D8
D7
RESET#
GND
CLK#
CLK
VDDQ
VDD
VREF
D6
D5
29
D4
28
To 12 Other Channels
0003G—05/21/02
Q7B
Q6B
VDDQ
Q5B
Q4B
Q3B
Q2B
Q1B
VDDQ
D1
D2
VDD
VDDQ
D3
56 pin VFQFN (MLF2)
ICSSSTV16859
General Description
The 13-bit-to-26-bit ICSSSTV16859 is a universal bus driver designed for 2.3V to 2.7V V
DD
operation and
SSTL_2 I/O levels, except for the LVCMOS RESET# input.
Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The
positive edge of CLK is used to trigger the data flow whereas CLK# is used to maintain sufficient noise margins
where as RESET#, an LVCMOS asynchronous signal, is intended for use at the time of power-up only.
ICSSSTV16859 supports low-power standby operation. A logic level “Low” at RESET# assures that all internal
registers and outputs (Q) are reset to the logic “Low” state, and all input receivers, data (D) and clock (CLK/
CLK#) are switched off. Please note that RESET# must always be supported with LVCMOS levels at a valid
logic state because VREF may not be stable during power-up.
To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET# must be
held at a logic “low” level during power up.
In the DDR DIMM application, RESET# is specified to be completely asynchronous with respect to CLK and
CLK#. Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power
standby state, the register will be cleared and the outputs will be driven to a logic “Low” level quickly relative
to the time to disable the differential input receivers. This ensures there are no glitches on the output. However,
when coming out of low-power standby state, the register will become active quickly relative to the time to
enable the differential input receivers. When the data inputs are at a logic level “low” and the clock is stable
during the “Low”-to-”High” transition of RESET# until the input receivers are fully enabled, the design ensures
that the outputs will remain at a logic “Low” level.
Pin Configuration (64-Pin TSSOP)
PIN NUMBER
1-5, 8-14, 16, 17, 19-25, 28-32
7, 15, 26, 34, 39, 43, 50, 54,
58, 63
6, 18, 27, 33, 38, 47, 59, 64
35, 36, 40-42, 44, 52, 53, 55-
57, 61, 62
48
49
37, 46, 60
51
45
PIN NAME
Q (13:1)
GND
VDDQ
D (13:1)
CLK
CLK#
VDD
RESET#
VREF
TYPE
OUTPUT
PWR
PWR
INPUT
INPUT
INPUT
PWR
INPUT
INPUT
Data output
Ground
Output supply voltage, 2.5V nominal
Data input
Positive master clock input
Negative master clock input
Core supply voltage, 2.5V nominal
Reset (active low)
Input reference voltage, 2.5V nominal
DESCRIPTION
Pin Configuration (56-Pin MLF2)
PIN NUMBER
1-8, 10-16, 18-22, 50-54, 56
37, 48
9, 17, 23, 27, 34, 44, 49, 55
24, 25, 28-31, 39-43, 46, 47
35
36
26, 33, 45
38
32
-
0003G—05/21/02
PIN NAME
Q (13:1)
GND
VDDQ
D (13:1)
CLK
CLK#
VDD
RESET#
VREF
Center PAD
TYPE
OUTPUT
PWR
PWR
INPUT
INPUT
INPUT
PWR
INPUT
INPUT
PWR
Data output
Ground
DESCRIPTION
Output supply voltage, 2.5V nominal
Data input
Positive master clock input
Negative master clock input
Core supply voltage, 2.5V nominal
Reset (active low)
Input reference voltage, 2.5V nominal
Ground (MLF2 package only)
2
ICSSSTV16859
Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . .
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . .
Input Voltage
1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage
1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Clamp Current . . . . . . . . . . . . . . . . . . . .
Output Clamp Current . . . . . . . . . . . . . . . . . . .
Continuous Output Current . . . . . . . . . . . . . . .
V
DD
, V
DDQ
or GND Current/Pin . . . . . . . . . . .
Package Thermal Impedance
3
...............
–65°C to +150°C
-0.5 to 3.6V
-0.5 to V
DD
+0.5
-0.5 to V
DDQ
+0.5
±50 mA
±50 mA
±50 mA
±100 mA
55°C/W
Notes:
1. The input and output negative voltage
ratings may be excluded if the input
and output clamp ratings are observed.
2. This current will flow only when the
output is in the high state level
V
0
>V
DDQ
.
3. The package thermal impedance is
calculated in accordance with
JESD 51.
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Recommended Operating Conditions
PARAMETER
V
DD
V
DDQ
V
REF
V
TT
V
I
V
IH (DC)
V
IH (AC)
V
IL (DC)
V
IL (DC)
V
IH
V
IL
V
ICR
V
ID
V
IX
I
OH
I
OL
T
A
1
DESCRIPTION
Supply Voltage
I/O Supply Voltage
Reference Voltage
Termination Voltage
Input Voltage
DC Input High Voltage
AC Input High Voltage
Data Inputs
DC Input Low Voltage
AC Input Low Voltage
Input High Voltage Level
RESET#
Input Low Voltage Level
Common mode Input Range
CLK, CLK#
Differential Input Voltage
Cross Point Voltage of Differential Clock
Pair
High-Level Output Current
Low-Level Output Current
Operating Free-Air Temperature
MIN
2.3
2.3
1.15
V
REF
- 0.04
0
V
REF
+ 0.15
V
REF
+ 0.31
TYP
2.5
2.5
1.25
V
REF
MAX
2.7
2.7
1.35
V
REF
+ 0.04
V
DDQ
UNITS
V
REF
- 0.15
V
REF
- 0.31
1.7
0.97
0.36
(V
DDQ
/2) - 0.2
0.7
1.53
V
(V
DDQ
/2) + 0.2
-20
20
70
mA
°C
0
Guarenteed by design, not 100% tested in production.
0003G—05/21/02
3
ICSSSTV16859
Electrical Characteristics - DC
T
A
= 0 - 70º C; V
DD
= 2.5 +/-0.2V, V
DDQ
=2.5 +/-0.2V; (unless otherwise stated)
SYMBOL
V
IK
V
OH
PARAMETERS
I
I
= -18mA
I
OH
= -100µA
I
OH
= -16mA
I
OL
= 100µA
I
OL
= 16mA
All Inputs
V
I
= V
DD
or GND
Standby (Static)
RESET# = GND
V
I
= V
IH(AC)
or V
IL(AC)
,
Operating (Static)
RESET# = V
DD
RESET# = V
DD
,
Dynamic operating
V
I
= V
IH(AC)
or V
IL(AC)
,
(clock only)
CLK and CLK# switching
50% duty cycle.
I
O
= 0
RESET# = V
DD
,
V
I
= V
IH(AC)
or V
IL (AC)
,
Dynamic Operating CLK and CLK# switching
(per each data input) 50% duty cycle. One data
input switching at half
clock frequency, 50%
duty cycle
Output High
I
OH
= -20mA
Output Low
I
OL
= 20mA
[r
OH
- r
OL
] each
I
O
= 20mA, T
A
= 25° C
separate bit
Data Inputs
V
I
= V
REF
±350mV
CLK and CLK#
V
ICR
= 1.25V, V
I(PP)
= 360mV
CONDITIONS
V
DDQ
2.3V
2.3V-2.7V
2.3V
2.3V-2.7V
2.3V
2.7V
V
DDQ
-
0.2
1.95
0.2
0.35
±5
0.01
50
MIN
TYP
MAX
-1.2
UNITS
V
V
OL
I
I
I
DD
µA
µA
mA
70
2.7V
µ/clock
MHz
I
DDD
30
µA/ clock
MHz/data
r
OH
r
OL
r
O(D)
C
i
2.3V-2.7V
2.3V-2.7V
2.5V
2.5V
7
7
13.5
13
20
20
4
Ω
Ω
Ω
pF
2.5
2.5
3.5
3.5
Notes:
1 - Guaranteed by design, not 100% tested in production.
0003G—05/21/02
4
ICSSSTV16859
Timing Requirements
1
(over recommended operating free-air temperature range, unless otherwise noted)
V
DDQ
= 2.5V ± 0.2V
SYMBOL
PARAMETERS
MIN
MAX
Clock frequency
200
f
clock
TSSOP
1.7
2.7
t
PD
Clock to output time
VFQFN (MLF2)
1.6
2.6
Reset to output time
5
t
RST
t
SL
Output slew rate
1
4
0.60
Setup time, fast slew rate
2 & 4
t
S
Data before CLK↑ , CLK#↓
3&4
0.80
Setup time, slow slew rate
0.40
Hold time, fast slew rate
2 & 4
T
h
Data after CLK↑ , CLK#↓
0.50
Hold time, slow slew rate
3 & 4
1 - Guaranteed by design, not 100% tested in production.
Notes:
2 - For data signal input slew rate of
≥
1V/ns.
3 - For data signal input slew rate of
≥
0.5V/ns and < 1V/ns.
4 - CLK, CLK# signals input slew rate of
≥
1V/ns.
UNITS
MHz
ns
ns
ns
V/ns
ns
ns
ns
ns
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted) (see Figure 1)
From
To
V
DD
= 2.5V ±0.2V
UNITS
SYMBOL
MIN
TYP
MAX
(Input)
(Output)
200
MHz
f
max
CLK, CLK# (TSSOP)
Q
1.7
2.3
2.7
ns
t
PD
CLK, CLK# (VFQFN[MLF2])
Q
1.6
2.1
2.6
ns
RESET#
Q
5
ns
t
phl
0003G—05/21/02
5
模拟与混合信号
