áç
OCTOBER 2003
ST16C1450/51
2.97V TO 5.5V UART
REV. 4.2.0
GENERAL DESCRIPTION
The ST16C1450, ST16C1451 series (here on
denoted as the 145X) is a universal asynchronous
receiver and transmitter (UART). The 145X is foot
print compatible to the SSI 73M1550 and SSI
73M2550 UART with one byte FIFO and higher
operating speed and lower access time. The 145X
provides enhanced UART functions with a modem
control interface, independent programmable baud
rate generators with clock rates to 1.5 Mbps. Onboard
status registers provide the user with error indications
and operational status. System interrupts and modem
control features may be tailored by external software
to meet specific user requirements. An internal loop-
back capability allows onboard diagnostics. The 145X
is available in a 28-pin PLCC/plastic-DIP 48-pin
,
TQFP packages. The Baud rate generator can be
configured for either crystal or external clock input
with the exception of the 28 pin 1451 package. An
external clock must be provided for the 28 pin 1451
package. Each package type, with the exception of
the 28 pin 1450, provides a buffered reset output that
can be controlled through user software. The 145X is
fabricated in an advanced CMOS process to achieve
low drain power and high speed requirements. The
ST16C145X is not compatible with the industry
standard 16450 and will not work with the standard
serial port driver in MS Windows (see pages 15-16 for
details). For a MS Windows compatible UART, see
the ST16C450.
FEATURES
•
Pin and functionally compatible to SSI 73M1550/
2550
•
1 byte Transmit FIFO (THR)
•
1 byte Receive FIFO with error tags (RHR)
•
Four levels of prioritized interrupts
•
Modem Control Signals (CTS#, RTS#, DSR#,
DTR#, RI#, CD#)
•
Programmable character lengths (5, 6, 7, 8) with
even, odd or no parity
•
Crystal or external clock input (except 28 pin
ST16C1451, external clock only)
•
1.5 Mbps Transmit/Receive operation (24 MHz)
with programmable clock control
•
Power Down Mode (50 uA at 3.3 V, 200 uA at 5 V)
•
Software controllable reset output
•
2.97 to 5.5 Volt operation
APPLICATIONS
•
Battery Operated Electronics
•
Internet Appliances
•
Handheld Terminal
•
Personal Digital Assistants
•
Cellular Phones DataPort
F
IGURE
1. B
LOCK
D
IAGRAM
T HR
A 2:A0
D 7:D0
IO R #
IO W #
C S#
D ata Bu s
In te rfac e
D TR # , R T S #
U A RT
C on figu ra tion
R eg s
M o de m C on tro l S ig na ls
D SR # , C T S #,
C D #, RI#
T ra ns m itter
TX
IN T
R ec e ive r
RHR
RX
B au d R ate G e n erator
R ES E T
R ST
X TA L 1/CL K
X TA L 2
C ry stal O sc /B u ffe r
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
ST16C1450/51
2.97V TO 5.5V UART
F
IGURE
2. ST16C1450 P
INOUTS
áç
REV. 4.2.0
48-TQFP PACKAGE
DSR#
VCC
N.C.
N.C.
N.C.
CD#
N.C.
N.C.
D3
D2
D1
D0
N
OTE
:
PINOUTS NOT TO SCALE
.
ACTUAL SIZE OF TQFP PACKAGE
IS SMALLER THAN PLCC PACKAGE
.
48
47
46
45
44
43
42
41
40
39
38
N.C.
N.C.
D4
D5
D6
D7
RX
TX
CS#
N.C.
N.C.
N.C.
1
2
3
4
5
6
37
36
35
34
33
32
31
N.C.
N.C.
CTS#
RESET
DTR#
RTS#
A0
N.C.
A1
A2
N.C.
N.C.
ST16C1450CQ48
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
30
29
28
27
26
25
28-PDIP PACKAGES
D0
D1
D2
D3
D4
1
2
3
4
28
27
26
25
VCC
CD#
DSR#
CTS#
RESET
DTR#
RTS#
A0
A1
A2
INT
RI#
IOR#
GND
XTAL1
XTAL2
RST
N.C.
N.C.
N.C.
GND
IOW#
IOR#
N.C.
RI#
INT
5
6
7
8
9
10
11
12
13
14
ST16C1450CP28
24
23
22
21
20
19
18
17
16
15
28-PLCC PACKAGES
26 DSR#
VCC
D3
D2
D1
D0
CD#
D5
D6
D7
RX
28
27
4
3
2
1
D4
D5
D6
D7
RX
TX
5
6
7
8
9
10
25
24
23
CTS#
RESET
DTR#
RTS#
A0
A1
A2
TX
CS#
XTAL1
XTAL2
IOW#
ST16C1450CJ28
22
21
20
19
CS# 11
12
13
14
15
16
17
RI#
18
INT
XTAL1
XTAL2
GND
IOW#
IOR#
2
áç
REV. 4.2.0
ST16C1450/51
2.97V TO 5.5V UART
F
IGURE
3. ST16C1451 P
INOUTS
48-TQFP PACKAGE
N
OTE
:
PINOUTS NOT TO SCALE
.
DSR#
ACTUAL SIZE OF TQFP PACKAGE
IS SMALLER THAN PLCC PACKAGE
.
VCC
N.C.
N.C.
N.C.
CD#
N.C.
38
48
47
46
45
44
43
42
41
40
39
N.C.
N.C.
D4
D5
D6
D7
RX
TX
CS#
N.C.
N.C.
N.C.
1
2
3
4
5
6
37
36
35
34
33
32
31
N.C.
D3
D2
D1
D0
N.C.
N.C.
CTS#
RESET
DTR#
RTS#
A0
N.C.
A1
A2
N.C.
N.C.
ST16C1451CQ48
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
30
29
28
27
26
25
28-PDIP PACKAGES
D0
D1
1
2
3
4
28
27
26
25
VCC
CD#
DSR#
CTS#
RESET
DTR#
RTS#
A0
A1
A2
INT
RST
RI#
IOR#
XTAL1
XTAL2
RST
N.C.
N.C.
N.C.
GND
IOW#
IOR#
N.C.
RI#
INT
D2
D3
D4
D5
5
6
7
8
9
10
11
12
13
14
ST16C1451CP28
24
23
22
21
20
19
18
17
16
15
28-PLCC PACKAGES
26 DSR#
VCC
CD#
D3
D2
D1
D0
D6
D7
RX
TX
28
D4
D5
D6
D7
RX
TX
27
4
3
2
1
5
6
7
8
9
10
25
24
23
CTS#
RESET
DTR#
RTS#
A0
A1
A2
CS#
CLK
IOW#
GND
ST16C1451CJ28
22
21
20
19
CS# 11
12
IOW# 13
14
15
16
17
RST
18
INT
CLK
GND
IOR#
RI#
3
ST16C1450/51
2.97V TO 5.5V UART
áç
REV. 4.2.0
ORDERING INFORMATION
O
PERATING
P
ART
N
UMBER
ST16C1450CP28
ST16C1450CJ28
ST16C1450CQ48
ST16C1451CP28
ST16C1451CJ28
ST16C1451CQ48
ST16C1450IP28
ST16C1450IJ28
ST16C1450IQ48
ST16C1451IP28
ST16C1451IJ28
ST16C1451IQ48
P
ACKAGE
28-Lead PDIP
28-Lead PLCC
48-Lead TQFP
28-Lead PDIP
28-Lead PLCC
48-Lead TQFP
28-Lead PDIP
28-Lead PLCC
48-Lead TQFP
28-Lead PDIP
28-Lead PLCC
48-Lead TQFP
T
EMPERATURE
R
ANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
D
EVICE
S
TATUS
Discontinued. See the ST16C1450CQ48 for a replacement.
Active
Active
Discontinued. See the ST16C1450CQ48 for a replacement.
Discontinued. See the ST16C1450CQ48 for a replacement.
Discontinued. See the ST16C1450CQ48 for a replacement.
-40°C to +85°C Discontinued. See the ST16C1450IQ48 for a replacement.
-40°C to +85°C Active
-40°C to +85°C Active
-40°C to +85°C Discontinued. See the ST16C1450IQ48 for a replacement.
-40°C to +85°C Discontinued. See the ST16C1450IQ48 for a replacement.
-40°C to +85°C Discontinued. See the ST16C1450IQ48 for a replacement.
4
áç
REV. 4.2.0
ST16C1450/51
2.97V TO 5.5V UART
PIN DESCRIPTIONS
N
AME
28-P
IN
28-P
IN
28-P
IN
PDIP
PDIP PLCC
(1450) (1451) (1450)
28-P
IN
PLCC
(1451)
48-P
IN
TQFP
(145X)
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE
A0
A1
A2
D0
D1
D2
D3
D4
D5
D6
D7
IOR#
21
20
19
1
2
3
4
5
6
7
8
16
21
20
19
1
2
3
4
5
6
7
8
15
21
20
19
1
2
3
4
5
6
7
8
16
21
20
19
1
2
3
4
5
6
7
8
15
30
28
27
43
45
46
47
3
4
5
6
20
I
Address data lines [2:0]. A2:A0 selects internal UART’s
configuration registers.
I/O
Data bus lines [7:0] (bidirectional).
I
Input/Output Read (active low). The falling edge instigates
an internal read cycle and retrieves the data byte from an
internal register pointed by the address lines [A2:A0], places
it on the data bus to allow the host processor to read it on
the leading edge.
Input/Output Write (active low). The falling edge instigates
the internal write cycle and the rising edge transfers the
data byte on the data bus to an internal register pointed by
the address lines [A2:A0].
Chip Select input (active low). A logic 0 on this pin selects
the ST16C145X device.
Interrupt Output (three-state, active high). INT output
defaults to three-state mode and becomes active high when
MCR bit-3 is set to a logic 1. INT output becomes a logic
high level when interrupts are enabled in the interrupt
enable register (IER), and whenever the transmitter,
receiver, line and/or modem status register has an active
condition.
IOW#
14
13
14
13
17
I
CS#
INT
11
18
11
18
11
18
11
18
9
23
I
O
MODEM OR SERIAL I/O INTERFACE
TX
10
10
10
10
8
O
Transmit Data. This output is associated with individual
serial transmit channel data from the 145X. The TX signal
will be a logic 1 during reset, idle (no data), or when the
transmitter is disabled. During the local loopback mode, the
TX output pin is disabled and TX data is internally con-
nected to the UART RX input.
Receive Data. This input is associated with individual serial
channel data to the 145X. Normal received data input idles
at logic 1 condition. This input must be connected to its idle
logic state, logic 1, else the receiver may report “receive
break” and/or “error” condition(s).
RX
9
9
9
9
7
I
5
