ST16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
JANUARY 2011
REV. 4.4.1
GENERAL DESCRIPTION
The ST16C2550 (C2550) is a dual universal
asynchronous receiver and transmitter (UART). The
ST16C2550 is an improved version of the PC16550
UART with higher operating speed and faster access
times. The C2550 provides enhanced UART
functions with 16 byte FIFO’s, a modem control
interface, and data rates up to 4 Mbps. Onboard
status registers provide the user with error indications
and operational status. System interrupts and modem
control features may be tailored by external software
to meet specific user requirements. Independent
programmable baud rate generators are provided to
select transmit and receive clock rates from 50 bps to
4 Mbps. The Baud Rate Generator can be configured
for either crystal or external clock input. An internal
loopback capability allows onboard diagnostics. The
C2550 is available in a 44-pin PLCC and 48-pin
TQFP packages. The C2550 is fabricated in an
advanced CMOS process capable of operating from
2.97 volt to 5.5 volt power supply.
APPLICATIONS
FEATURES
Added feature in devices with top mark date code
of "A2 YYWW" and newer:
■
5 Volt Tolerant Inputs
•
Pin-to-pin compatible to Exar’s ST16C2450,
XR16L2550 and XR16L2750
•
Pin-to-pin compatible to TI’s TL16C752B on the 48-
TQFP package
•
Pin alike XR16C2850 48-TQFP package but
without CLK8/16, CLKSEL and HDCNTL inputs
•
2 independent UART channels
■
■
■
■
■
■
■
•
Portable Appliances
•
Telecommunication Network Routers
•
Ethernet Network Routers
•
Cellular Data Devices
•
Factory Automation and Process Controls
F
IGURE
1. ST16C2550 B
LOCK
D
IAGRAM
Up to 4 Mbps with external clock of 64 MHz
Up to 1.5 Mbps data rate with a 24 MHz crystal
frequency
16 byte Transmit FIFO to reduce the bandwidth
requirement of the external CPU
16 byte Receive FIFO with error tags to reduce
the bandwidth requirement of the external CPU
4 selectable Receive FIFO interrupt trigger
levels
Modem control signals (CTS#, RTS#, DSR#,
DTR#, RI#, CD#)
Programmable character lengths (5, 6, 7, 8)
with even, odd, or no parity
•
Crystal oscillator or external clock input
•
48-TQFP and 44-PLCC packages
A2:A0
D7:D0
IOR#
IOW#
CSA#
CSB#
INTA
INTB
TXRDYA#
TXRDYB#
RXRDYA#
RDRXYB#
Reset
8-bit Data
Bus
Interface
UART Channel A
UART
Regs
BRG
16 Byte TX FIFO
TX & RX
16 Byte RX FIFO
2.97V to 5.5V
GND
TXA, RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
UART Channel B
(same as Channel A)
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
XTAL1
XTAL2
Crystal Osc/Buffer
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
ST16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
F
IGURE
2. P
IN
O
UT
A
SSIGNMENT
TXRDYA#
REV. 4.4.1
DSRA#
VCC
RIA#
CTSA#
38
CDA#
48
40
45
43
42
47
46
44
41
39
37
NC
D4
D3
D2
D1
D0
D5
D6
D7
RXB
RXA
TXRDYB#
TXA
TXB
OP2B#
1
2
3
4
5
6
7
8
9
36
35
34
33
RESET
DTRB#
DTRA#
RTSA#
OP2A#
RXRDYA#
INTA
INTB
A0
A1
A2
NC
ST16C2550
48-pin TQFP
32
31
30
29
28
27
26
25
D0
D1
D2
D3
D4
D5
D6
D7
RXB
RXA
1
2
3
4
5
6
7
40
39
38
37
36
35
34
VCC
RIA#
CDA#
DSRA#
CTSA#
RESET
DTRB#
DTRA#
RTSA#
OP2A#
INTA
INTB
A0
A1
A2
CTSB#
RTSB#
RIB#
DSRB#
IOR#
CSA# 10
CSB# 11
NC 12
15
18
19
20
22
13
16
17
21
23
CTSB#
14
24
NC
GND
DSRB#
RXRDYB#
RTSB#
CDB#
XTAL2
XTAL1
IOW#
IOR#
RIB#
9
10
11
12
13
14
15
16
17
18
19
20
ST16C2550CP40
8
33
32
31
30
29
28
27
26
25
24
23
22
21
TXRDYA#
DSRA#
CTSA#
TXA
TXB
OP2B#
39
38
37
36
RESET
DTRB#
DTRA#
RTSA#
44
43
42
CDA#
RIA#
VCC
D4
D3
D2
D1
D0
41
40
6
5
4
3
2
1
D5
D6
D7
RXB
RXA
7
8
9
10
11
CSA#
CSB#
XTAL1
XTAL2
IOW#
CDB#
GND
TXRDYB# 12
TXA
TXB
13
14
ST16C2550
44-pin PLCC
35 OP2A#
34
33
32
31
RXRDYA#
INTA
INTB
A0
OP2B# 15
CSA# 16
CSB# 17
XTAL1 18
XTAL2 19
IOW# 20
CDB# 21
GND 22
RXRDYB# 23
IOR# 24
DSRB# 25
RIB# 26
RTSB# 27
CTSB# 28
30 A1
29
A2
2
ST16C2550
REV. 4.4.1
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
ORDERING INFORMATION
O
PERATING
P
ART
N
UMBER
ST16C2550CP40
ST16C2550CJ44
P
ACKAGE
40-Lead PDIP
44-Lead PLCC
T
EMPERATURE
R
ANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
D
EVICE
S
TATUS
Active. See the ST16C2550CQ48 for new designs.
Active
Active
Active. See the ST16C2550IQ48 for new designs.
Active
Active
ST16C2550CQ48 48-Lead TQFP
ST16C2550IP40
ST16C2550IJ44
ST16C2550IQ48
40-Lead PDIP
44-Lead PLCC
48-Lead TQFP
3
ST16C2550
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 4.4.1
PIN DESCRIPTIONS
Pin Description
N
AME
40-PDIP
P
IN
#
44-PLCC
P
IN
#
48-TQFP
P
IN
#
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
26
27
28
8
7
6
5
4
3
2
1
21
29
30
31
9
8
7
6
5
4
3
2
24
26
27
28
3
2
1
48
47
46
45
44
19
I
Address data lines [2:0]. These 3 address lines select one
of the internal registers in UART channel A/B during a
data bus transaction.
Data bus lines [7:0] (bidirectional).
IO
I
Input/Output Read Strobe (active low). The falling edge
instigates an internal read cycle and retrieves the data
byte from an internal register pointed to by the address
lines [A2:A0]. The data byte is placed on the data bus to
allow the host processor to read it on the rising edge.
Input/Output Write Strobe (active low). The falling edge
instigates an internal write cycle and the rising edge
transfers the data byte on the data bus to an internal reg-
ister pointed by the address lines.
UART channel A select (active low) to enable UART
channel A in the device for data bus operation.
UART channel B select (active low) to enable UART
channel B in the device for data bus operation.
UART channel A Interrupt output. The output state is
defined by the user and through the software setting of
MCR[3]. INTA is set to the active mode and OP2A# out-
put to a logic 0 when MCR[3] is set to a logic 1. INTA is
set to the three state mode and OP2A# to a logic 1 when
MCR[3] is set to a logic 0 (default). See MCR[3].
UART channel B Interrupt output. The output state is
defined by the user and through the software setting of
MCR[3]. INTB is set to the active mode and OP2B# out-
put to a logic 0 when MCR[3] is set to a logic 1. INTB is
set to the three state mode and OP2B# to a logic 1 when
MCR[3] is set to a logic 0 (default). See MCR[3].
UART channel A Transmitter Ready (active low). The out-
put provides the TX FIFO/THR status for transmit channel
A. See
Table 2.
If it is not used, leave it unconnected.
UART channel A Receiver Ready (active low). This out-
put provides the RX FIFO/RHR status for receive channel
A. See
Table 2.
If it is not used, leave it unconnected.
IOW#
18
20
15
I
CSA#
CSB#
INTA
14
15
30
16
17
33
10
11
30
I
I
O
INTB
29
32
29
O
TXRDYA#
-
1
43
O
RXRDYA#
-
34
31
O
4
ST16C2550
REV. 4.4.1
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
Pin Description
N
AME
TXRDYB#
40-PDIP
P
IN
#
-
44-PLCC
P
IN
#
12
48-TQFP
P
IN
#
6
T
YPE
O
D
ESCRIPTION
UART channel B Transmitter Ready (active low). The out-
put provides the TX FIFO/THR status for transmit channel
B. See
Table 2.
If it is not used, leave it unconnected.
UART channel B Receiver Ready (active low). This out-
put provides the RX FIFO/RHR status for receive channel
B. See
Table 2.
If it is not used, leave it unconnected.
RXRDYB#
-
23
18
O
MODEM OR SERIAL I/O INTERFACE
TXA
RXA
11
10
13
11
7
5
O
I
UART channel A Transmit Data. If it is not used, leave it
unconnected.
UART channel A Receive Data. Normal receive data
input must idle at logic 1 condition. If it is not used, tie it to
VCC or pull it high via a 100k ohm resistor.
UART channel A Request-to-Send (active low) or general
purpose output. If it is not used, leave it unconnected.
UART channel A Clear-to-Send (active low) or general
purpose input. This input should be connected to VCC
when not used. This input has no effect on the UART.
UART channel A Data-Terminal-Ready (active low) or
general purpose output. If it is not used, leave it uncon-
nected.
UART channel A Data-Set-Ready (active low) or general
purpose input. This input should be connected to VCC
when not used. This input has no effect on the UART.
UART channel A Carrier-Detect (active low) or general
purpose input. This input should be connected to VCC
when not used. This input has no effect on the UART.
UART channel A Ring-Indicator (active low) or general
purpose input. This input should be connected to VCC
when not used. This input has no effect on the UART.
Output Port 2 Channel A - The output state is defined by
the user and through the software setting of MCR[3].
INTA is set to the active mode and OP2A# output to a
logic 0 when MCR[3] is set to a logic 1. INTA is set to the
three state mode and OP2A# to a logic 1 when MCR[3] is
set to a logic 0. See MCR[3]. This output should not be
used as a general output else it will disturb the INTA out-
put functionality. If it is not used at all, leave it uncon-
nected.
UART channel B Transmit Data. If it is not used, leave it
unconnected.
UART channel B Receive Data. Normal receive data
input must idle at logic 1 condition. If it is not used, tie it to
VCC or pull it high via a 100k ohm resistor.
UART channel B Request-to-Send (active low) or general
purpose output. If it is not used, leave it unconnected.
RTSA#
CTSA#
32
36
36
40
33
38
O
I
DTRA#
33
37
34
O
DSRA#
37
41
39
I
CDA#
38
42
40
I
RIA#
39
43
41
I
OP2A#
31
35
32
O
TXB
RXB
12
9
14
10
8
4
O
I
RTSB#
24
27
22
O
5
51单片机
