®
ST20-GP6
GPS PROCESSOR
FEATURES
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Figure 1. Package
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Application specific features
•
12 channel GPS correlation DSP hardware,
ST20 CPU (for control and position
calculations) and memory on one chip
•
no TCXO required
•
RTCA-SC159 / WAAS / EGNOS supported
GPS performance
•
accuracy
- stand alone with SA on <100m, SA off <30m
- differential <1m
- surveying <1cm
•
time to first fix
- autonomous start 90s
- cold start 45s
- warm start 7s
- obscuration 1s
Enhanced 32-bit VL-RISC CPU - C2 core
•
16/33/50 MHz processor clock
•
25 MIPS at 33 MHz
•
fast integer/bit operations
64 Kbytes on-chip SRAM
128 Kbytes on-chip ROM
Programmable memory interface
•
4 separately configurable regions
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8/16-bits wide
•
support for mixed memory
•
2 cycle external access
Programmable UART (ASC)
Parallel I/O
Vectored interrupt subsystem
Diagnostic control unit
Power management
•
low power operation
•
power down modes
Professional toolset support
•
ANSI C compiler/link driver and libraries
•
Debugging/profiling and simulation tools
Technology
•
Static clocked 50 MHz design
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3.3 V, sub micron technology
100 pin PQFP package
JTAG Test Access Port
PQFP100
Table 1. Order Codes
Part Number
ST20GP6X33S
Package
PQFP100
Figure 2. Block Diagram
GPS
radio
ST20-GP6
12 channel GPS
hardware DSP
ST20
CPU
Low
power
controller
Real time
clock/calendar
Interrupt
controller
Serial
communications
2 UART (ASC)
Programmable
memory
interface
Parallel
input/output
.
16
.
.
64K
SRAM
Diagnostic
control unit
128K optional
mask ROM
Test
access port
APPLICATIONS
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Global Positioning System (GPS) receivers
Car navigation systems
Fleet management systems
Time reference for telecom systems
October 2004
Rev. 2
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ST20-GP6
Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ST20-GP6 architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital signal processing module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
5
7
11
DSP module registers ........................................................................................................................... 13
4
Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
4.2
4.3
4.4
4.5
4.6
19
Registers ............................................................................................................................................... 19
Processes and concurrency ................................................................................................................. 20
Priority ................................................................................................................................................... 22
Process communications ...................................................................................................................... 23
Timers ................................................................................................................................................... 23
Traps and exceptions ........................................................................................................................... 24
5
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
5.2
5.3
5.4
5.5
5.6
Interrupt vector table .............................................................................................................................
Interrupt handlers ..................................................................................................................................
Interrupt latency ....................................................................................................................................
Preemption and interrupt priority ..........................................................................................................
Restrictions on interrupt handlers .........................................................................................................
Interrupt configuration registers ............................................................................................................
30
31
31
32
32
33
33
6
Interrupt level controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1
6.2
37
Interrupt assignments ........................................................................................................................... 37
Interrupt level controller registers ......................................................................................................... 37
7
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1
7.2
7.3
40
Instruction cycles .................................................................................................................................. 40
Instruction characteristics ..................................................................................................................... 41
Instruction set tables ............................................................................................................................. 42
8
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1
8.2
8.3
51
System memory use ............................................................................................................................. 51
Boot ROM ............................................................................................................................................. 52
Internal peripheral space ...................................................................................................................... 52
9
Memory subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1
9.2
55
SRAM ................................................................................................................................................... 55
ROM ..................................................................................................................................................... 55
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ST20-GP6
10 Programmable memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1
10.2
10.3
10.4
10.5
10.6
EMI signal descriptions .........................................................................................................................
External accesses .................................................................................................................................
MemWait ...............................................................................................................................................
EMI configuration registers ...................................................................................................................
Boot source ...........................................................................................................................................
Default configuration .............................................................................................................................
56
58
59
60
62
65
65
11 Low power controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1
11.2
66
Low power control ................................................................................................................................. 66
Low power configuration registers ........................................................................................................ 67
12 Real time clock and watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1
12.2
12.3
12.4
70
Power supplies ..................................................................................................................................... 70
Real time clock ..................................................................................................................................... 70
Watchdog timer ..................................................................................................................................... 70
RTC/WDT configuration registers ......................................................................................................... 71
13 System services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.1
13.2
13.3
73
Reset, initialization and debug .............................................................................................................. 73
Bootstrap .............................................................................................................................................. 73
Clocks ................................................................................................................................................... 73
14 Diagnostic controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.1
14.2
14.3
14.4
14.5
14.6
Diagnostic hardware .............................................................................................................................
Access features ....................................................................................................................................
Software debugging features ................................................................................................................
Controlling the diagnostic controller ......................................................................................................
Peeking and poking the host from the target ........................................................................................
Abortable instructions ...........................................................................................................................
75
75
76
77
79
80
80
15 UART interface (ASC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.1
15.2
15.3
15.4
15.5
Functionality ..........................................................................................................................................
Timeout mechanism .............................................................................................................................
Baud rate generation ............................................................................................................................
Interrupt control ....................................................................................................................................
ASC configuration registers ..................................................................................................................
82
82
85
85
86
88
16 Parallel input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.1
94
PIO Ports0-1 ......................................................................................................................................... 94
17 Configuration register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
96
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ST20-GP6
18 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
19 GPS Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
19.1
19.2
Accuracy ............................................................................................................................................... 106
Time to first fix ...................................................................................................................................... 107
20 Timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
20.1
20.2
20.3
20.4
20.5
EMI timings ........................................................................................................................................... 108
Reset timings ........................................................................................................................................ 110
PIO timings ........................................................................................................................................... 111
ClockIn timings ..................................................................................................................................... 112
JTAG IEEE 1149.1 timings ................................................................................................................... 113
21 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
22 Package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
22.1
22.2
ST20-GP6 package pinout ................................................................................................................... 116
100 pin PQFP package dimensions ..................................................................................................... 119
23 Test access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
24 Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
25
Revision History. . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
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ST20-GP6
1
Introduction
The ST20-GP6 is an application-specific single chip micro using the ST20 CPU with
microprocessor style peripherals added on-chip. It incorporates DSP hardware for processing the
signals from GPS (Global Positioning System) satellites.
The twelve channel GPS correlation DSP hardware is designed to handle twelve satellites, two of
which can be initialized to support the RTCA-SC159 specification for WAAS (Wide Area
Augmentation Service) and EGNOS (European Geostationary Navigation Overlay System)
services.
The ST20-GP6 has been designed to minimize system costs and reduce the complexity of GPS
systems. It offers all hardware DSP and microprocessor functions on one chip and provides
sufficient on-chip RAM and ROM. The entire analogue section, RF and clock generation are
available on a companion chip. Thus, a complete GPS system is possible using just two chips, see
Figure 1.1.
Antenna
ST20-GP6
STB5600
Radio
Single chip
DSP
ASIC
CPU
UART
Driver
(optional)
Parallel
I/O
Low
cost
crystal
No TCXO
Real
time
clock
Parallel I/O
Watchdog
timer
optional
mask ROM
RAM
Figure 1.1 GPS system
The ST20-GP6 supports large values of frequency offset, allowing the use of a very low cost
oscillator, thus saving the cost of a Temperature Controlled Crystal Oscillator (TCXO).
The CPU and software have access to the part-processed signal to enable accelerated acquisition
time.
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