512 K x 32 Static RAM
SYS32512ZK/LK - 010/012/015
Issue 5.0 June 1999
Description
The SYS32512 is a 512K x 8 SRAM module in a ZIP
(ZK) or SIMM (LK & LKXA) packages with access
times of 12 and 15ns, with 10ns parts under
development. The device is available to
commercial and industrial temperature grade.
The LK SIMM package is designed for standard
SIMM sockets. The LKXA is designed to fit both
angled and standard sockets.
Block Diagram
A0~A18
/WE
/OE
512K x 8
SRAM
/CS1
512K x 8
D0~7
SRAM
/CS2
512K x 8
D8~15
Features
• Access times of 10, 12 and 15ns.
• 5V + 10%.
• Commercial and Industrial temperature grades
• 72 pin ZIP and SIMM packages.
• Industry standard footprint.
• Power dissipation.
• Operating Power
(32 Bit) 4.62W (max)
• Low power standby. (TTL) 1.32W (max)
(CMOS) 330mW (max)
• Completely Static Operation.
/CS3
SRAM
D16~23
512K x 8
SRAM
/CS4
D24~D31
Pin Definition
See page 2.
Pin Functions
Description
Address Input
Data Input/Output
Chip Select
Presence Detect
Write Enable
Output Enable
No Connect
Power
Ground
Signal
A0~A18
D0~D31
/CS1~4
PD0~3
/WE
/OE
NC
V
CC
V
SS
Package Details
Plastic 72 Pin ZIP (ZK)
Max. Dimensions (mm) - 97.80 x 20.61 x 5.90
Plastic 72 Pin SIMM (LK)
Max. Dimensions (mm) - 108.08 x 15.00 x 5.25
Plastic 72 Pin SIMM (LKXA)
Max. Dimensions (mm) - 108.08 x 20.32 x 4.55
Pin Definition - SYS32512 ZK/LK/LKXA
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Signal
NC
NC
PD2
PD3
V
SS
PD0
PD1
D0
D8
D1
D9
D2
D10
D3
D11
V
CC
A0
A7
A1
A8
A2
A9
D12
D4
D13
D5
D14
D6
D15
D7
V
SS
/WE
A15
A14
/CS2
/CS1
Pin
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Signal
/CS4
/CS3
A17
A16
/OE
V
SS
D24
D16
D25
D17
D26
D18
D27
D19
A3
A10
A4
A11
A5
A12
V
CC
A13
A6
D20
D28
D21
D29
D22
D30
D23
D31
V
SS
A18
NC
NC
NC
Note
ZK : PD1=GND, PDO=PD2=PD3=OPEN
PAGE 2
Issue 5.0 June 1999
Absolute Maximum Ratings
(1)
DC Operating Conditions
Parameter
Voltage on any pin relative to V
SS
Power Dissipation
Storage Temperature
Symbol
V
T
P
T
T
STG
(2)
Min
-0.3
to
4.0
-55
to
Max
+7.0
Unit
V
W
+125
O
C
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability
(2) V
T
can be -2.0V pulse of less than 2ns.
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
(Commercial
)
(Industrial)
Symbol
V
CC
V
IH
V
IL
T
A
T
AI
Min
4.5
2.2
-0.3
0
-40
Typ
5.0
-
-
-
-
Max
5.5
V
CC
+0.3
0.8
70
85
Unit
V
V
V
O
O
C
C
(I Suffix)
DC Electrical Characteristics
(V
CC
=5V+10%, T
A
=0
O
C to 70
O
C)
Parameter
Input Leakage Current
Output Leakage
Current
Average Supply Current
Standby Supply Current
Address,
/OE, /WE
Worst
Case
32 Bit
TTL
CMOS
Symbol Test Condition
I
LI
0V < V
IN
< V
CC
Min
-8
Typ
-
Max
8
Unit
µ
A
µ
A
I
LO
/CS=V
IH
,V
I/O
=GND to V
CC
Min. Cycle, /CS=V
IL
, V
IN
=V
IH
or V
IL
, I
OUT
=OmA
/CS=V
IH
/CS >V
CC
-0.2V, 0.2V
>V
IN
>V
CC
-0.2V
I
OL
=8.0mA
I
OH
=-4.0mA
-8
-
8
I
CC1
I
SB1
I
SB2
V
OL
V
OH
-
-
-
-
2.4
-
-
-
-
-
840
240
60
0.4
-
mA
mA
mA
V
V
Output Voltage Low
Output Voltage High
Notes (1) /CS1~4 inputs operate simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for
8 bit mode.
(2) Typical Values are at V
CC
=5.0V, T
A
=25
O
C and specified loading. /CS above refers to /CS1~4
PAGE 3
Issue 5.0 June 1999
Capacitance
(V
CC
= 5.0V, T
A
= 25
O
C)
P aram eter
Input C apacitan ce, (
Address, /O E, /W E)
Input C apacitan ce, (
O ther)
O utpu t C apacita nce,
8 bit m ode (w orst case)
S ym b ol
C
IN 1
C
IN 2
C
I/O
T est C ondition
V
IN
= 0V
V
IN
= 0V
V
I/O
= 0V
M in
-
-
-
T yp
-
-
-
M ax
32
7
40
U nit
pF
pF
pF
Note : These Parameters are calculated not measured.
Test Conditions
•
•
•
•
•
Input pulse levels : 0V to 3.0V
Input rise and fall times : 3ns
Input and Output timing reference levels : 1.5V
Output Load : See Load Diagram.
V
CC
= 5V+10%
Output Load
I/O Pin
166Ω
1.76V
30pF
Operation Truth Table
/CS
H
L
L
L
L
/OE /WE
X
L
H
L
H
X
H
L
L
H
Data Pins
High Impedence
Data Out
Data In
Data In
High Impedence
Supply Current
I
SB1
,I
SB2
I
CC1
I
CC1
I
CC1
I
SB1
,I
SB2
Mode
Standby
Read
Write
Write
High Z
Notes : H=V
IH
: L=V
IL
: X=V
IH
or V
IL
PAGE 4
Issue 5.0 June 1999
Read Cycle
10
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold From Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
Output Disable to Output in High Z
12
15
AC Operating Conditions
Symbol Min Max Min Max Min Max Units
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
t
OLZ
t
CHZ
t
OHZ
10
-
-
-
3
3
0
0
0
-
10
10
5
-
-
-
5
5
12
-
-
-
3
3
0
0
0
-
12
12
6
-
-
-
6
6
15
-
-
-
3
3
0
0
0
-
15
15
7
-
-
-
7
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
10
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold time from Write Time
Output Active from End of Write
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
12
15
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min Max Min Max Min Max
10
7
7
0
7
0
0
5
0
3
-
-
-
-
-
-
5
-
-
-
12
8
8
0
8
0
0
6
0
3
-
-
-
-
-
-
6
-
-
-
15
10
10
0
10
0
0
7
0
3
-
-
-
-
-
-
10
-
-
-
Under Development
PAGE 5
Issue 5.0 June 1999
