首页 > 器件类别 > 数模转换芯片

TPC116S4

Quad 16-/14-/12-Bit, Low Power, High Performance DACs

器件类别:数模转换芯片   

厂商名称:思瑞浦微电子科技(3PEAK INCORPORATED)

厂商官网:http://www.3peakic.com.cn

下载文档
器件参数
参数名称
属性值
Part Number
TPC116S4
Status
Production
Resolution(bit)
16
Settling Time(uS)
14
CH
4
Interface
SPI
Reference
External
Voltage Output Range(V)
0~Vef
INL(LSB, Max)
±16
DNL(LSB, Max)
±1
Offset Error(mV,Max)
30
Gain Error(% of FSR, Max)
0.3
D to A Glitch Impulse(nV-sec)
0.1
VDD (V)
2.7~5.5
IDD(uA/CH, typ)
90
Temp Range(℃)
-40~125
Package
TSSOP-16
文档预览
TPC116S4/ TPC112S4
 
 
Quad  16‐/12‐Bit,  Low  Power,  High  Performance  DACs
Description
The TPC116S4/TPC112S4 are pin compatible 16-bit
and 12-bit digital-to-analog converter, these series
product are four channels, low power, buffered
voltage-out DACs and are guaranteed monotonic by
design. The devices use a precision external reference
applied through the high resistance input for rail-to-rail
operation and low system power consumption.
The
TPC116S4/ TPC112S4
accepts a wide 2.7V to 5.5V
supply
voltage range. The parts incorporate a power-on
Features
Quad, 16-/12-Bit Pin Compatible DACs
TPC116S4: 16bit
TPC112S4: 12bit
Low Power Consumption (800μA typ)
Differential Nonlinearity: ±1LSB(max)
Glitch Energy: 2nV-s
Power-On Reset to Zero
Supply Range: 2.7V to 5.5V
Buffered Rail-to-Rail Output Operation
Safe Power-On Reset (POR) to Zero DAC Output
Fast 30MHz, 3-Wire,
SPI/QSPI/MICROWIRE-Compatible Serial Interface
Schmitt-Trigger Inputs for Direct Optocoupler
Interface
SYNC Interrupt Facility
High Performance Drop-In Compatible With
TLV5614
Available in TSSOP-16 Package
reset circuit to ensure that the DAC output powers up to
0 V and remains there until a valid write takes place.
The TPC116S4/ TPC112S4 on-chip precision output
amplifier allows rail-to-rail output swing to be achieved.
For remote sensing applications, the output amplifier’s
inverting input is available to the user. The TPC116S4/
TPC112S4 use a versatile 3-wire serial interface that
operates at clock rates up to 30 MHz and is compatible
with standard SPI®, QSPI™, MICROWIRE™, and DSP
interface standards.
The TPC116S4/ TPC112S4 are available in a small
size 16-pin TSSOP package, all package are specified
over the -40°C to +125°C extended industrial
temperature range.
Applications
Gain and Offset Adjustment
Process Control and Servo Loops
Programmable voltage and current sources
Programmable attenuators
Automatic Test Equipment
3PEAK and the 3PEAK logo are registered trademarks of
3PEAK INCORPORATED. All other trademarks are the property of
their respective owners.
Package Information
(Top View)
Block diagram of one DAC
 
Order Information
www.3peakic.com.cn
Rev. 0
1
 
TPC116S4/ TPC112S4
 
Model Name
TPC112S4
TPC116S4*
Order Number
TPC112S4-TR
TPC116S4-TR
 
Quad 16‐/12‐Bit, Low Power, High Performance DACs 
Package
16-Pin TSSOP
16-Pin TSSOP
Transport Media, Quantity
Tape and Reel, 3,000
Tape and Reel, 3,000
Marking
Information
112S4
116S4
* Sample is not ready, can be provided in 2 months.
Absolute Maximum Ratings
Note 1
Supply Voltage: V
+
– V
Note 2
............................7.0V
Input Voltage............................. V
– 0.3 to V
+
+ 0.3
Input Current: +IN, –IN
Note 3
.......................... ±20mA
Output Short-Circuit Duration
Note 4
…......... Indefinite
Operating Temperature Range........–40°C to 125°C
Maximum Junction Temperature................... 150°C
Storage Temperature Range.......... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ......... 260°C
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and lifetime.
Note 2:
The supplies must be established simultaneously, with, or before, the application of any input signals.
Note 3:
The inputs are protected by ESD protection diodes to each power supply. If the input extends more than 500mV beyond the power supply, the input
current should be limited to less than 10mA.
Note 4:
A heat sink may be required to keep the junction temperature below the absolute maximum. This depends on the power supply voltage and how many
amplifiers are shorted. Thermal resistance varies with the amount of PC board metal connected to the package. The specified values are for short traces
connected to the leads.
ESD, Electrostatic Discharge Protection
Symbol
HBM
CDM
Parameter
Human Body Model ESD
Charged Device Model ESD
Condition
ANSI/ESDA/JEDEC JS-001
ANSI/ESDA/JEDEC JS-002
Minimum Level
8
2
Unit
kV
kV
Thermal Resistance
Package Type
16-Pin TSSOP
θ
JA
180
θ
JC
35
Unit
°C/W
2
 
Rev. 0
www.3peakic.com.cn
        
TPC116S4/ TPC112S4
Quad 16‐/12‐Bit, Low Power, High Performance DACs
Electrical Characteristics
(V
DD
= 5V, V
REF
= 5V, C
L
= 100pF, R
L
= 10kΩ, T
A
= -40°C to +105°C, unless otherwise noted. Typical values are at T
A
= +25°C.)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC ACCURACY (Note 5)
N
INL
DNL
OE
Resolution
Integral Nonlinearity
Differential Nonlinearity
Zero Offset Error
Full-Scale Offset Error
Offset-Error Drift
GE
Gain Error
Gain Temperature Coefficient
REFERENCE INPUT
V
REF
R
REF
Reference-Input Voltage Range
Reference-Input Impedance
No load (typical)
10 kΩ load
DC Output Impedance
C
L
R
L
Capacitive Load (Note 8)
Resistive Load (Note 8)
Short-Circuit Current
Power-Up Time
DIGITAL INPUTS (SCLK, DIN, SYNC)
V
IH
V
IL
I
IN
C
IN
Input High Voltage
Input Low Voltage
Input Leakage Current
Input Capacitance
V
DD
= 5V
V
DD
= 3.3V
V
DD
= 5V
V
DD
= 3.3V
V
IN
= 0V or V
DD
±5
1
2
1.5
0.6
0.4
±10
V
V
V
V
μA
pF
V
DD
= 5.5V
From power-down mode
Series resistance = 0Ω
Series resistance = 1kΩ
5
35
25
0.2
0.1
0.1
15
0.5
333
V
REF
V
REF
-0.
1
V
DD
V
kΩ
-0.3
-30
TPC112S4
TPC116S4
TPC112S4 (12-bit) (Note 6)
TPC116S4 (16-bit) (Note 6)
TPC112S4 (12-bit) (Note 6)
TPC116S4 (16-bit) (Note 6)
12
16
-2
-16
-1
-1
±0.25
±8
±0.05
±0.5
6.5
0
±1
±0.13
±2
0.3
2
16
1
1
30
30
Bits
LSB
LSB
mV
mV
μV/°C
%FS
ppmFS/
°C
DAC OUTPUT
Output Voltage Range
V
nF
μF
kΩ
mA
μs
Electrical Characteristics(continued)
(V
DD
= 5V, V
REF
= 5V, C
L
= 100pF, R
L
= 10kΩ, T
A
= -40°C to +105°C, unless otherwise noted. Typical values are at T
A
= +25°C.
www.3peakic.com.cn
Rev. 0
3
 
TPC116S4/ TPC112S4
 
SYMBOL
V
HYS
SR
BW
PARAMETER
Hysteresis Voltage
Voltage-Output Slew Rate
Voltage-Output Settling Time
Reference -3dB Bandwidth
Digital Feedthrough
DAC Glitch Impulse
Output Noise
Integrated Output Noise
POWER REQUIREMENTS
V
DD
I
DD
Supply Voltage
 
Quad 16‐/12‐Bit, Low Power, High Performance DACs 
CONDITIONS
MIN
TYP
0.15
Positive and negative
1/4 scale to 3/4 scale, to
0.5 LSB,
12-bit
Hex code = 800 (TPC112S4),
Hex code = 8000 (TPC116S4)
Code = 0, all digital inputs from 0V to VDD,
SCLK < 50MHz
Major code transition
10kHz
0.1Hz to 10Hz
2.7
V
DD
= 5V , No load; all digital inputs at 0V or
Supply Current
V
DD
,
supply
current
only;
excludes
0.8
1.5
mA
reference input current, midscale
V
DD
= 3.3V , No load; all digital inputs at 0V
I
DD
Supply Current
Power-Down Supply Current
or V
DD
, supply current only; excludes
reference input current, midscale
No load, all digital inputs at 0V or V
DD
500
μA
Note 5:
Linearity is tested within 20mV of GND and V
DD
.
Note 6:
Gain and offset is tested within 100mV of GND and V
DD
.
Note 7:
Guaranteed by design; not production tested.
Note 8:
All timing specifications measured with V
IL
= V
GND
, V
IH
= V
DD
.
0.5
1
mA
1
14
100
0.5
2
90
25
5.5
MAX
UNITS
V
V/μs
μs
kHz
nV·s
nV·s
nV/√Hz
μV
P-P
V
DYNAMIC PERFORMANCE (Note 8)
www.3peakic.com.cn
Rev. 0
4
 
        
TPC116S4/ TPC112S4
Quad 16‐/12‐Bit, Low Power, High Performance DACs
Serial Write Operation
 
Figure 1. 16-Bit Serial-Interface Timing Diagram (TPC112S4)
DIN
DIN23
DIN22
t
DS
t
DH
SCLK
t
CSH0
t
CSS0
SYNC
t
CSPW
t
CL
t
CSF
1
2
3
4
5
t
CH
DIN21
DIN20
DIN19
t
CP
DIN18
DIN17
DIN16
DIN2
DIN1
DIN0
DIN23
6
7
8
22
23
t
CH1
t
CSA
24
1
  
Figure 2. 24-Bit Serial-Interface Timing Diagram (TPC116S4)
TIMING CHARACTERISTICS (Figures 1,2 and 3)
SYMBOL
f
SCLK
t
CH
t
CL
t
CSS0
t
CSH0
t
CSH1
t
CSA
t
CSF
t
DS
t
DH
t
CSPW
t
CLPW
t
CSC
PARAMETER
Serial Clock Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
SYNC Fall to SCLK Fall Setup Time
SYNC Fall to SCLK Fall Hold Time
SYNC Rise to SCLK Fall Hold Time
SYNC Rise to SCLK Fall
SCLK Fall to SYNC Fall
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
SYNC Pulse-Width High
SYNC Pulse-Width Low
SYNC Rise to SYNC Fall
100
5
4.5
20
20
20
CONDITIONS
MIN
0
8
8
8
0
0
12
TYP
MAX
30
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
www.3peakic.com.cn
Rev. 0
5
 
查看更多>